Difficulty: Medium
Correct Answer: Have both their operands in the main store.
Explanation:
Introduction / Context:Instruction-set architectures (ISAs) classify instructions by where operands are fetched and where results are written. Understanding Storage-to-Storage (memory-to-memory) operations helps distinguish them from Register-to-Register and Register-to-Storage formats, which impact performance, code density, and CPU design.
Given Data / Assumptions:
Concept / Approach:Storage-to-Storage instructions fetch both source operands directly from memory and typically store the result back to memory, minimizing explicit register use. This differs from Register-to-Storage (one operand in a register, one in memory) and Register-to-Register (both operands in registers).
Step-by-Step Solution:
1) Define categories: S–S, R–S, and R–R based on operand locations.2) For S–S: both operands are in memory; result often returns to memory.3) For R–S: one register and one memory operand; result usually in register (store writes to memory).4) For R–R: both operands in registers; result kept in a register.Verification / Alternative check:Examining an ISA manual that lists “MOVS”, “CMPS”, or block memory ops confirms that some instructions read two memory locations and update memory directly without explicit general-purpose register destinations.
Why Other Options Are Wrong:
Common Pitfalls:Assuming all modern CPUs forbid memory-to-memory ALU ops. Some CISC ISAs retain them; RISC designs prefer register-based operations for pipeline simplicity.
Final Answer:Have both their operands in the main store.
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