Q: Pulse-triggered flip-flops are identified by a bubble on the Q output terminal. Assess the accuracy of this identification in standard logic symbols.

Introduction / Context: Logic symbols convey device behavior visually. Triangles, bubbles, and other markings have standardized meanings. Misreading these symbols can cause misinterpretation of timing and polarity in flip-flop usage. Given Data / Assumptions: A small triangle on the clock input denotes edge-sensitive triggering. A bubble on a pin denotes logical inversion at that pin. Q and ~Q (Q-bar) outputs may be shown; a bubble on Q means an inverted output, not a trigger style. Concept / Approach: “Pulse-triggered” is not a standard label identified by a bubble on Q. In symbols, the triangle at the clock indicates edge-triggering; a bubble on the clock indicates negative-edge sensitivity. A bubble on the Q output simply indicates the output is the complement of Q (often labeled ~Q), not any special triggering mechanism. Step-by-Step Solution: Identify edge sensitivity: look for a small triangle on the clock input.Identify negative-edge devices: a bubble on the clock combined with the triangle.Recognize complementary outputs: a bubble on Q pin marks inversion (Q-bar), independent of triggering.Conclude that a bubble on Q does not denote pulse triggering. Verification / Alternative check: Standard textbooks and datasheets show D, JK, and T flip-flops with triangle/bubble on the clock to indicate edge and polarity; outputs are labeled Q and ~Q, with a bubble indicating inversion only. Why Other Options Are Wrong: Calling it “Correct” confuses output inversion with trigger style. Negative-edge devices are indicated at the clock input, not at Q. Vendor artwork still follows the convention separating output polarity indicators from clock edge indicators. Common Pitfalls: Assuming any bubble equals “active-low timing” everywhere; bubbles can indicate inversion for inputs or outputs, and their meaning depends on the pin they adorn. Final Answer: Incorrect

Q: Propagation delay definitions — meaning of tPLH for flip-flop outputs Determine whether the statement is correct: “tPLH is measured from the triggering edge of the clock to the LOW-to-HIGH transition at the output.”

Introduction / Context: Manufacturers specify timing with two complementary propagation delays: tPLH (low-to-high) and tPHL (high-to-low). For clocked devices such as flip-flops, these delays are measured from the active clock edge to the resulting transition at Q. Understanding these labels is crucial for timing closure and clock-speed calculations. Given Data / Assumptions: An edge-triggered flip-flop is clocked by a defined active edge. tPLH corresponds to an output change from logic 0 to logic 1. Timing is measured to the 50% crossing of input and output waveforms unless otherwise stated in the datasheet. Concept / Approach: tPLH is the time interval between the reference instant (typically the 50% point of the triggering clock edge) and the 50% point of the output's rising transition. Similarly, tPHL is measured for a falling output transition. These metrics quantify the internal response time and help compute data-path delays and setup/hold slacks in synchronous systems. Step-by-Step Solution: Identify the triggering clock edge (rising or falling by device specification).Mark the reference (50%) crossing of that edge as t=0.Observe the output transition; if it is LOW→HIGH, measure to its 50% point.The measured interval is tPLH, by definition. Verification / Alternative check: Consult any standard logic family datasheet: the timing diagrams label tPLH/tPHL exactly as described, for both combinational and sequential devices. Why Other Options Are Wrong: “Incorrect” misstates the conventional definition. “Only for asynchronous inputs” is wrong; the measurement reference is the clock edge, not asynchronous input changes. “Only for combinational gates” is false; the same naming convention applies to clocked devices with the clock edge as reference. Common Pitfalls: Confusing which transition (output or input) the L/H refers to; measuring from wrong reference points; ignoring clock-to-Q differences among families. Final Answer: Correct

Q: J–K flip-flop toggle behavior — effect of a TOGGLE (T) command State whether the following is correct: “A TOGGLE input to a J–K flip-flop causes the Q and Q̄ outputs to switch to their opposite states.”

Introduction / Context: J–K flip-flops are general-purpose sequential elements. When both J and K are asserted (J=1, K=1) at the active clock edge, the device toggles, meaning Q changes to Q̄ and vice versa. Many devices expose this function as a dedicated T (toggle) input by internally tying J and K together. Given Data / Assumptions: An edge-triggered J–K flip-flop is clocked properly and meets setup/hold constraints. No asynchronous inputs (PRESET/CLEAR) are overriding the state. Toggle condition corresponds to J=K=1 or an external T command translated to that condition. Concept / Approach: J=0,K=0 holds state; J=1,K=0 sets Q=1; J=0,K=1 resets Q=0; J=1,K=1 toggles Q. Therefore, under a toggle directive the outputs invert each active clock edge, implementing divide-by-2 counting when driven by a periodic clock. Step-by-Step Solution: Apply T (or J=K=1) with the clock at its active edge.Flip-flop recognizes the toggle condition.Q becomes Q̄(previous), and Q̄ becomes Q(previous).On subsequent active edges, the process repeats, producing a square-wave at half the clock frequency. Verification / Alternative check: Build a divide-by-2 using a J–K with J=K=1; scope shows Q toggling each clock. Why Other Options Are Wrong: “Incorrect” ignores the standard J–K truth table. Preset/Clear dominance is an orthogonal feature; toggle still works when they are inactive. Clock level vs. edge triggering does not negate the definition of the toggle case. Common Pitfalls: Violating setup/hold around the edge causes metastability instead of clean toggling; forgetting asynchronous inputs override normal operation. Final Answer: Correct

Q: Pulse-triggered vs. level-triggered devices — are they the same? Assess the statement: “Pulse-triggered or level-triggered devices are the same.”

Introduction / Context: Digital storage elements come in different triggering styles. Level-triggered devices (transparent latches) pass input changes while the enable level is active; pulse-triggered (edge-like) or edge-triggered devices capture data at a brief interval or an instant. Equating them leads to timing errors and race conditions. Given Data / Assumptions: Level-triggered latch: transparent when enable level is asserted; opaque otherwise. Pulse-triggered: responds during a narrow pulse; edge-triggered: responds at a transition (rising/falling edge). All observe setup/hold around their sampling window. Concept / Approach: Latches can propagate glitches and allow input changes to flow to outputs during the entire enable level, which can create unintended feedback if not staged properly. Edge/pulse-triggered elements minimize transparency, sampling data once per cycle, enabling straightforward synchronous pipelines with well-defined clock boundaries. Step-by-Step Solution: Compare timing diagrams: latch output follows input during enable; flip-flop output updates only near the edge/pulse.Analyze hazard: combinational feedback can oscillate during latch transparency; edge-triggered devices break this path.Conclude they are functionally different and used for different timing goals. Verification / Alternative check: Design a two-phase latch system versus one-phase edge-triggered pipeline; behavior differs despite identical clock periods. Why Other Options Are Wrong: “Correct,” “equivalent at low frequency,” and “equivalent at 50% duty” ignore qualitative transparency differences; frequency or duty cycle does not remove the fundamental timing model distinctions. Common Pitfalls: Assuming latch-based circuits are drop-in replacements for edge-based ones; forgetting time-borrowing properties of latches versus fixed edge timing. Final Answer: Incorrect

Q: Using a latch for switch debouncing — contact-bounce eliminator role Evaluate: “A latch can act as a contact-bounce eliminator.”

Introduction / Context: Mechanical switches bounce: a single press causes rapid on-off transitions before settling. Digital systems must convert this chattering waveform into a single, clean transition. Latches and simple RS configurations are classic debouncing techniques, often with RC networks or Schmitt triggers to shape edges. Given Data / Assumptions: Switch contacts exhibit multiple transitions within a few milliseconds. A latch has two stable states and can be driven by appropriately conditioned signals. Power rails and reference levels are solid; no excessive noise beyond contact bounce. Concept / Approach: An SR latch with cross-coupled NOR or NAND gates can be driven by two switch positions so that only one valid assertion is seen at a time. Once set or reset, the latch holds its state despite brief chatter on the mechanical contacts, effectively eliminating multiple transitions at its output. Additional RC filtering or Schmitt-trigger buffering can improve noise immunity. Step-by-Step Solution: Map the switch poles to produce clean SET and RESET signals (often using a DPDT or steering diodes).Feed these into an SR latch (NOR-based for active-high or NAND-based for active-low logic).On a press, the first valid transition asserts SET/RESET; the latch changes state.Subsequent bounces do not change the state because the opposite input is inactive. Verification / Alternative check: Oscilloscope traces show a chattering switch input while the latch output presents one clean edge. Many vendor app notes present latch-based debouncers as standard solutions. Why Other Options Are Wrong: “Incorrect” ignores established practice. Requiring Schmitt inputs or edge-triggered clocks is unnecessary; they can help but are not mandatory for latch-based debouncing. Common Pitfalls: Driving both S and R simultaneously; neglecting proper pull-ups/pull-downs; forgetting that SR latches can become invalid if both inputs assert. Final Answer: Correct

Q: Monostable (one-shot) multivibrator — need for an external trigger Assess the statement: “A one-shot is a special type of multivibrator that must be triggered to produce each output pulse.”

Introduction / Context: Multivibrators are categorized by stability: astable (no stable state), monostable (one stable state), and bistable (two stable states). A monostable, commonly called a one-shot, produces a single pulse of defined width in response to a trigger. Understanding this behavior is key to designing timers, pulse stretchers, and debounce circuits. Given Data / Assumptions: The device has one stable state and returns to it automatically. An external triggering event initiates the temporary unstable state. Pulse width is set by internal or external timing elements (RC, digital counters, etc.). Concept / Approach: Upon receiving a valid trigger, the one-shot output changes state and stays there for a predetermined period T. After T elapses, the circuit self-resets to the stable state. There are retriggerable and non-retriggerable versions; both still require a trigger for the first pulse. Step-by-Step Solution: Hold the device in its stable state with no trigger.Apply a trigger edge/level; output asserts for interval T.After T, output returns to the stable level automatically.If retriggerable, a new trigger during T extends the pulse; if not, it is ignored. Verification / Alternative check: Timing diagrams and datasheets (e.g., 74HC123 retriggerable one-shot) show the dependence on triggers to produce pulses. Why Other Options Are Wrong: “Incorrect” contradicts the definition of monostable. Limitations like “only for non-retriggerable” or “only when RC timing is used” are unnecessary; trigger dependence is fundamental regardless of timing implementation. Common Pitfalls: Confusing monostable with astable oscillators; improper trigger conditioning leading to multiple pulses; not debouncing mechanical triggers. Final Answer: Correct

Q: Edge-triggered flip-flops — timing of input sampling and output change Judge the statement: “With edge-triggered flip-flops, data enter on the leading clock edge but the output does not change until the trailing edge.”

Introduction / Context: Edge-triggered flip-flops sample inputs at a specific clock transition and then update outputs after a propagation delay referenced to that same edge. The idea that the output waits for the opposite clock edge mixes up edge-triggered behavior with two-phase master–slave latch operation. Given Data / Assumptions: The device is an edge-triggered flip-flop (rising or falling edge). Setup and hold times are met around the active edge. Clock-to-Q propagation delay (tPLH/tPHL) defines when Q settles after the edge. Concept / Approach: At the active edge, the flip-flop captures inputs and begins internal transitions. The output reflects the new state after a short delay (nanoseconds), not at the opposite clock edge. Master–slave latches internally use two non-overlapping phases but still present a single-edge interface; the public Q does not wait for the trailing edge in true edge-triggered implementations. Step-by-Step Solution: Identify the specified active edge (e.g., rising edge).Ensure D/J/K inputs are stable for tSU/tH around this edge.Observe that Q updates after the edge by tPLH/tPHL, completing well before the next opposite edge.Therefore, the statement claiming change only at the trailing edge is incorrect. Verification / Alternative check: Datasheet timing diagrams show clock-to-Q referenced to the same edge. Simulation with a standard D or J–K flip-flop confirms immediate (delayed) response after the active edge. Why Other Options Are Wrong: “Correct” contradicts standard timing. “True only for master–slave” and “true only with gated clocks” add conditions that still do not defer Q until the opposite edge in edge-triggered devices. Common Pitfalls: Confusing transparent latching intervals with edge capture; ignoring propagation delay and thus expecting instantaneous change at the edge. Final Answer: Incorrect

Q: VHDL component instantiation syntax — label, colon, and entity reference Evaluate the statement: “Each VHDL component instance is given a name followed by a semicolon and then the name of the library primitive.”

Introduction / Context: Accurate VHDL syntax is essential for structural designs. Instances are labeled and associated with entities or components via a specific form that uses a colon, not a semicolon, and proper library/entity references. Misstating this leads to compilation errors and confusion about libraries and primitives. Given Data / Assumptions: We are instantiating an entity or component in VHDL. Typical forms include: label : entity work.my_ent(arch) port map(…); or label : my_comp port map(…); Library/USE clauses make entities visible, but there is no “name followed by a semicolon” pattern between label and entity. Concept / Approach: The correct syntax is label : entity library.entity_name (optional architecture), or label : component_name if using component declarations. The colon separates the instance label and the design unit being instantiated; a semicolon terminates the entire statement at the end, not between label and entity. Step-by-Step Solution: Write a label (e.g., u1).Place a colon then the entity or component name (e.g., u1 : entity work.foo).Provide generic map/port map associations.Terminate the statement with a semicolon after the port map, per VHDL syntax. Verification / Alternative check: Compile a small structural example; the compiler rejects the “label; entity …” form and accepts the “label : entity …” form. Why Other Options Are Wrong: “Correct” misstates the delimiter. The qualifiers about structural code or configurations do not change the colon requirement. Common Pitfalls: Forgetting library/USE clauses; mixing component and direct entity instantiation; misplacing the semicolon. Final Answer: Incorrect

Question 1

The 7475 is a classic TTL/CMOS IC that implements four transparent D latches (a 4-bit bistable latch) within a single package. Evaluate this identification.

Accepted Answer

Introduction / Context: Device numbering in the 74xx family can be confusing. The 7475 (and its CMOS variants) is historically referenced as a 4-bit D latch device, commonly used for temporary data storage and bus interfacing with level-sensitive transparency control. Given Data / Assumptions: “Transparent” means Q follows D while enable is active; data is latched when enable is inactive. Four independent D latches share control pins as specified by the datasheet. Outputs may include complementary pins depending on subfamily. Concept / Approach: A D latch differs from a D flip-flop: it is level-sensitive (gated), not edge-triggered. The 7475 embodies this by allowing data to flow through when the gate (enable) is active, then holding the last value when the gate is inactive. Step-by-Step Solution: Enable HIGH (typical) → Q tracks D.Enable LOW → Q holds the last D value seen while enabled.Repeat for four channels to store a 4-bit value or four independent signals.Use multiple packages to scale to 8 or 16 bits as needed. Verification / Alternative check: Cross-reference with standard 74xx family tables: 7475 (quad latch) vs 7474 (dual edge-triggered D flip-flop) illustrates the latch vs flip-flop distinction. Why Other Options Are Wrong: It is not an edge-triggered device; thus “Correct only for edge-triggered” is wrong. Tri-state capabilities are separate features on bus latches, not defining characteristics of the 7475 identification. Common Pitfalls: Confusing 7475 with 7474 or octal latches like 74HC373. Always check the family code for latch versus flip-flop behavior. Final Answer: Correct

Question 2

In VHDL, when an output port's value must be read back within the same entity (feedback usage), a special designation or modeling approach is required to make the feedback legal and synthesizable.

Accepted Answer

Introduction / Context: VHDL port modes control how signals are driven and read within an entity. Designers sometimes want to read an output value inside the entity (for feedback or internal decisions). Understanding how to model this correctly is important for legality and synthesis portability. Given Data / Assumptions: Standard port modes: in, out, inout, buffer (and linkage in VHDL-2008). Many synthesis tools discourage buffer and prefer internal signals. Goal: allow internal reading of a value that is also driven to an output pin. Concept / Approach: Best practice avoids using port mode buffer. Instead, declare an internal signal that carries the intended output value, read it internally as needed, and then assign this signal to an out port. This modeling approach is the “special designation” in practice: separate internal signal plus out port assignment. Step-by-Step Solution: Declare signal q_int : std_logic; within the architecture.Drive q_int in processes/functions where feedback is needed.Assign output port: Q <= q_int; allowing internal reads of q_int anywhere.Synthesize; tools infer proper logic while maintaining legal port usage. Verification / Alternative check: Many coding guidelines explicitly recommend avoiding buffer in favor of an internal signal driving an out port, improving tool compatibility. Simulation and synthesis behave consistently with this pattern. Why Other Options Are Wrong: It is not limited to simulation; synthesis also requires careful modeling. Bidirectional pins (inout) are for external tri-state buses, not generic internal feedback. Common Pitfalls: Using buffer indiscriminately, or attempting to read an out port directly in pre-2008 VHDL versions, causing compilation or synthesis issues. The internal-signal approach is robust and portable. Final Answer: Correct

Question 3

Pulse-triggered flip-flops are identified by a bubble on the Q output terminal. Assess the accuracy of this identification in standard logic symbols.

Accepted Answer

Introduction / Context: Logic symbols convey device behavior visually. Triangles, bubbles, and other markings have standardized meanings. Misreading these symbols can cause misinterpretation of timing and polarity in flip-flop usage. Given Data / Assumptions: A small triangle on the clock input denotes edge-sensitive triggering. A bubble on a pin denotes logical inversion at that pin. Q and ~Q (Q-bar) outputs may be shown; a bubble on Q means an inverted output, not a trigger style. Concept / Approach: “Pulse-triggered” is not a standard label identified by a bubble on Q. In symbols, the triangle at the clock indicates edge-triggering; a bubble on the clock indicates negative-edge sensitivity. A bubble on the Q output simply indicates the output is the complement of Q (often labeled ~Q), not any special triggering mechanism. Step-by-Step Solution: Identify edge sensitivity: look for a small triangle on the clock input.Identify negative-edge devices: a bubble on the clock combined with the triangle.Recognize complementary outputs: a bubble on Q pin marks inversion (Q-bar), independent of triggering.Conclude that a bubble on Q does not denote pulse triggering. Verification / Alternative check: Standard textbooks and datasheets show D, JK, and T flip-flops with triangle/bubble on the clock to indicate edge and polarity; outputs are labeled Q and ~Q, with a bubble indicating inversion only. Why Other Options Are Wrong: Calling it “Correct” confuses output inversion with trigger style. Negative-edge devices are indicated at the clock input, not at Q. Vendor artwork still follows the convention separating output polarity indicators from clock edge indicators. Common Pitfalls: Assuming any bubble equals “active-low timing” everywhere; bubbles can indicate inversion for inputs or outputs, and their meaning depends on the pin they adorn. Final Answer: Incorrect

Question 4

Edge-triggered J–K flip-flops — clarity of sampling instant State whether the statement is correct or incorrect: “Edge-triggered J–K flip-flops make it hard for design engineers to know when to accept (sample) input data.”

Accepted Answer

Introduction / Context: Edge-triggered flip-flops are widely used because they define an exact instant at which input data are sampled. The claim that they make it “hard to know when to accept input data” conflicts with their design purpose. This item checks your understanding of timing behavior for edge-triggered J–K flip-flops and why they simplify, not complicate, data acceptance. Given Data / Assumptions: The device is an edge-triggered J–K flip-flop (often represented with a triangle on the clock input). Inputs J and K are sampled at a specific clock edge (rising or falling as specified). Standard timing specs apply: setup time (tSU) and hold time (tH) around the active edge; propagation delay tPLH/tPHL from clock edge to output response. Concept / Approach: Edge-triggered devices capture data only at the defined active edge. Designers ensure input signals meet setup/hold windows around that edge. After the edge, the output changes after a finite propagation delay. This model provides a clear “sampling instant,” greatly simplifying synchronous design compared with level-triggered (transparent) latches that can pass glitches while enabled. Step-by-Step Solution: Identify active edge (e.g., rising edge for a device with a triangle symbol and no bubble).Guarantee J and K are stable for at least tSU before the edge and tH after the edge.After the edge, the flip-flop output updates after tPLH or tPHL depending on its previous state and inputs.Therefore, the sampling moment is explicit, not ambiguous. Verification / Alternative check: Timing diagrams show a narrow capture instant at the clock edge. Static timing analysis in synchronous design is built around these edges and tSU/tH constraints, confirming the predictability of data acceptance. Why Other Options Are Wrong: “Correct” contradicts the role of edge triggering. “Only true for negative-edge devices” is incorrect; edge polarity does not add ambiguity. “True only for master–slave types” is also incorrect; master–slave or single-edge behavior still samples at a defined edge. Common Pitfalls: Confusing edge-triggered flip-flops with level-sensitive latches; ignoring setup/hold leading to metastability; assuming output updates exactly at the edge rather than after propagation delay. Final Answer: Incorrect

Question 5

Propagation delay definitions — meaning of tPLH for flip-flop outputs Determine whether the statement is correct: “tPLH is measured from the triggering edge of the clock to the LOW-to-HIGH transition at the output.”

Accepted Answer

Introduction / Context: Manufacturers specify timing with two complementary propagation delays: tPLH (low-to-high) and tPHL (high-to-low). For clocked devices such as flip-flops, these delays are measured from the active clock edge to the resulting transition at Q. Understanding these labels is crucial for timing closure and clock-speed calculations. Given Data / Assumptions: An edge-triggered flip-flop is clocked by a defined active edge. tPLH corresponds to an output change from logic 0 to logic 1. Timing is measured to the 50% crossing of input and output waveforms unless otherwise stated in the datasheet. Concept / Approach: tPLH is the time interval between the reference instant (typically the 50% point of the triggering clock edge) and the 50% point of the output's rising transition. Similarly, tPHL is measured for a falling output transition. These metrics quantify the internal response time and help compute data-path delays and setup/hold slacks in synchronous systems. Step-by-Step Solution: Identify the triggering clock edge (rising or falling by device specification).Mark the reference (50%) crossing of that edge as t=0.Observe the output transition; if it is LOW→HIGH, measure to its 50% point.The measured interval is tPLH, by definition. Verification / Alternative check: Consult any standard logic family datasheet: the timing diagrams label tPLH/tPHL exactly as described, for both combinational and sequential devices. Why Other Options Are Wrong: “Incorrect” misstates the conventional definition. “Only for asynchronous inputs” is wrong; the measurement reference is the clock edge, not asynchronous input changes. “Only for combinational gates” is false; the same naming convention applies to clocked devices with the clock edge as reference. Common Pitfalls: Confusing which transition (output or input) the L/H refers to; measuring from wrong reference points; ignoring clock-to-Q differences among families. Final Answer: Correct

Question 6

J–K flip-flop toggle behavior — effect of a TOGGLE (T) command State whether the following is correct: “A TOGGLE input to a J–K flip-flop causes the Q and Q̄ outputs to switch to their opposite states.”

Accepted Answer

Introduction / Context: J–K flip-flops are general-purpose sequential elements. When both J and K are asserted (J=1, K=1) at the active clock edge, the device toggles, meaning Q changes to Q̄ and vice versa. Many devices expose this function as a dedicated T (toggle) input by internally tying J and K together. Given Data / Assumptions: An edge-triggered J–K flip-flop is clocked properly and meets setup/hold constraints. No asynchronous inputs (PRESET/CLEAR) are overriding the state. Toggle condition corresponds to J=K=1 or an external T command translated to that condition. Concept / Approach: J=0,K=0 holds state; J=1,K=0 sets Q=1; J=0,K=1 resets Q=0; J=1,K=1 toggles Q. Therefore, under a toggle directive the outputs invert each active clock edge, implementing divide-by-2 counting when driven by a periodic clock. Step-by-Step Solution: Apply T (or J=K=1) with the clock at its active edge.Flip-flop recognizes the toggle condition.Q becomes Q̄(previous), and Q̄ becomes Q(previous).On subsequent active edges, the process repeats, producing a square-wave at half the clock frequency. Verification / Alternative check: Build a divide-by-2 using a J–K with J=K=1; scope shows Q toggling each clock. Why Other Options Are Wrong: “Incorrect” ignores the standard J–K truth table. Preset/Clear dominance is an orthogonal feature; toggle still works when they are inactive. Clock level vs. edge triggering does not negate the definition of the toggle case. Common Pitfalls: Violating setup/hold around the edge causes metastability instead of clean toggling; forgetting asynchronous inputs override normal operation. Final Answer: Correct

Question 7

Pulse-triggered vs. level-triggered devices — are they the same? Assess the statement: “Pulse-triggered or level-triggered devices are the same.”

Accepted Answer

Introduction / Context: Digital storage elements come in different triggering styles. Level-triggered devices (transparent latches) pass input changes while the enable level is active; pulse-triggered (edge-like) or edge-triggered devices capture data at a brief interval or an instant. Equating them leads to timing errors and race conditions. Given Data / Assumptions: Level-triggered latch: transparent when enable level is asserted; opaque otherwise. Pulse-triggered: responds during a narrow pulse; edge-triggered: responds at a transition (rising/falling edge). All observe setup/hold around their sampling window. Concept / Approach: Latches can propagate glitches and allow input changes to flow to outputs during the entire enable level, which can create unintended feedback if not staged properly. Edge/pulse-triggered elements minimize transparency, sampling data once per cycle, enabling straightforward synchronous pipelines with well-defined clock boundaries. Step-by-Step Solution: Compare timing diagrams: latch output follows input during enable; flip-flop output updates only near the edge/pulse.Analyze hazard: combinational feedback can oscillate during latch transparency; edge-triggered devices break this path.Conclude they are functionally different and used for different timing goals. Verification / Alternative check: Design a two-phase latch system versus one-phase edge-triggered pipeline; behavior differs despite identical clock periods. Why Other Options Are Wrong: “Correct,” “equivalent at low frequency,” and “equivalent at 50% duty” ignore qualitative transparency differences; frequency or duty cycle does not remove the fundamental timing model distinctions. Common Pitfalls: Assuming latch-based circuits are drop-in replacements for edge-based ones; forgetting time-borrowing properties of latches versus fixed edge timing. Final Answer: Incorrect

Question 8

Using a latch for switch debouncing — contact-bounce eliminator role Evaluate: “A latch can act as a contact-bounce eliminator.”

Accepted Answer

Introduction / Context: Mechanical switches bounce: a single press causes rapid on-off transitions before settling. Digital systems must convert this chattering waveform into a single, clean transition. Latches and simple RS configurations are classic debouncing techniques, often with RC networks or Schmitt triggers to shape edges. Given Data / Assumptions: Switch contacts exhibit multiple transitions within a few milliseconds. A latch has two stable states and can be driven by appropriately conditioned signals. Power rails and reference levels are solid; no excessive noise beyond contact bounce. Concept / Approach: An SR latch with cross-coupled NOR or NAND gates can be driven by two switch positions so that only one valid assertion is seen at a time. Once set or reset, the latch holds its state despite brief chatter on the mechanical contacts, effectively eliminating multiple transitions at its output. Additional RC filtering or Schmitt-trigger buffering can improve noise immunity. Step-by-Step Solution: Map the switch poles to produce clean SET and RESET signals (often using a DPDT or steering diodes).Feed these into an SR latch (NOR-based for active-high or NAND-based for active-low logic).On a press, the first valid transition asserts SET/RESET; the latch changes state.Subsequent bounces do not change the state because the opposite input is inactive. Verification / Alternative check: Oscilloscope traces show a chattering switch input while the latch output presents one clean edge. Many vendor app notes present latch-based debouncers as standard solutions. Why Other Options Are Wrong: “Incorrect” ignores established practice. Requiring Schmitt inputs or edge-triggered clocks is unnecessary; they can help but are not mandatory for latch-based debouncing. Common Pitfalls: Driving both S and R simultaneously; neglecting proper pull-ups/pull-downs; forgetting that SR latches can become invalid if both inputs assert. Final Answer: Correct

Question 9

Monostable (one-shot) multivibrator — need for an external trigger Assess the statement: “A one-shot is a special type of multivibrator that must be triggered to produce each output pulse.”

Accepted Answer

Introduction / Context: Multivibrators are categorized by stability: astable (no stable state), monostable (one stable state), and bistable (two stable states). A monostable, commonly called a one-shot, produces a single pulse of defined width in response to a trigger. Understanding this behavior is key to designing timers, pulse stretchers, and debounce circuits. Given Data / Assumptions: The device has one stable state and returns to it automatically. An external triggering event initiates the temporary unstable state. Pulse width is set by internal or external timing elements (RC, digital counters, etc.). Concept / Approach: Upon receiving a valid trigger, the one-shot output changes state and stays there for a predetermined period T. After T elapses, the circuit self-resets to the stable state. There are retriggerable and non-retriggerable versions; both still require a trigger for the first pulse. Step-by-Step Solution: Hold the device in its stable state with no trigger.Apply a trigger edge/level; output asserts for interval T.After T, output returns to the stable level automatically.If retriggerable, a new trigger during T extends the pulse; if not, it is ignored. Verification / Alternative check: Timing diagrams and datasheets (e.g., 74HC123 retriggerable one-shot) show the dependence on triggers to produce pulses. Why Other Options Are Wrong: “Incorrect” contradicts the definition of monostable. Limitations like “only for non-retriggerable” or “only when RC timing is used” are unnecessary; trigger dependence is fundamental regardless of timing implementation. Common Pitfalls: Confusing monostable with astable oscillators; improper trigger conditioning leading to multiple pulses; not debouncing mechanical triggers. Final Answer: Correct

Question 10

Edge-triggered flip-flops — timing of input sampling and output change Judge the statement: “With edge-triggered flip-flops, data enter on the leading clock edge but the output does not change until the trailing edge.”

Accepted Answer

Introduction / Context: Edge-triggered flip-flops sample inputs at a specific clock transition and then update outputs after a propagation delay referenced to that same edge. The idea that the output waits for the opposite clock edge mixes up edge-triggered behavior with two-phase master–slave latch operation. Given Data / Assumptions: The device is an edge-triggered flip-flop (rising or falling edge). Setup and hold times are met around the active edge. Clock-to-Q propagation delay (tPLH/tPHL) defines when Q settles after the edge. Concept / Approach: At the active edge, the flip-flop captures inputs and begins internal transitions. The output reflects the new state after a short delay (nanoseconds), not at the opposite clock edge. Master–slave latches internally use two non-overlapping phases but still present a single-edge interface; the public Q does not wait for the trailing edge in true edge-triggered implementations. Step-by-Step Solution: Identify the specified active edge (e.g., rising edge).Ensure D/J/K inputs are stable for tSU/tH around this edge.Observe that Q updates after the edge by tPLH/tPHL, completing well before the next opposite edge.Therefore, the statement claiming change only at the trailing edge is incorrect. Verification / Alternative check: Datasheet timing diagrams show clock-to-Q referenced to the same edge. Simulation with a standard D or J–K flip-flop confirms immediate (delayed) response after the active edge. Why Other Options Are Wrong: “Correct” contradicts standard timing. “True only for master–slave” and “true only with gated clocks” add conditions that still do not defer Q until the opposite edge in edge-triggered devices. Common Pitfalls: Confusing transparent latching intervals with edge capture; ignoring propagation delay and thus expecting instantaneous change at the edge. Final Answer: Incorrect

Question 11

VHDL component instantiation syntax — label, colon, and entity reference Evaluate the statement: “Each VHDL component instance is given a name followed by a semicolon and then the name of the library primitive.”

Accepted Answer

Introduction / Context: Accurate VHDL syntax is essential for structural designs. Instances are labeled and associated with entities or components via a specific form that uses a colon, not a semicolon, and proper library/entity references. Misstating this leads to compilation errors and confusion about libraries and primitives. Given Data / Assumptions: We are instantiating an entity or component in VHDL. Typical forms include: label : entity work.my_ent(arch) port map(…); or label : my_comp port map(…); Library/USE clauses make entities visible, but there is no “name followed by a semicolon” pattern between label and entity. Concept / Approach: The correct syntax is label : entity library.entity_name (optional architecture), or label : component_name if using component declarations. The colon separates the instance label and the design unit being instantiated; a semicolon terminates the entire statement at the end, not between label and entity. Step-by-Step Solution: Write a label (e.g., u1).Place a colon then the entity or component name (e.g., u1 : entity work.foo).Provide generic map/port map associations.Terminate the statement with a semicolon after the port map, per VHDL syntax. Verification / Alternative check: Compile a small structural example; the compiler rejects the “label; entity …” form and accepts the “label : entity …” form. Why Other Options Are Wrong: “Correct” misstates the delimiter. The qualifiers about structural code or configurations do not change the colon requirement. Common Pitfalls: Forgetting library/USE clauses; mixing component and direct entity instantiation; misplacing the semicolon. Final Answer: Incorrect

Question 12

Flip-flop asynchronous controls — are PRESET and CLEAR normally synchronous? Judge the statement: “PRESET and CLEAR inputs are normally synchronous.”

Accepted Answer

Introduction / Context: Many flip-flops provide PRESET (set) and CLEAR (reset) inputs in addition to clocked data inputs. These controls are widely used for initialization and emergency forcing of states. Understanding whether they are synchronous (honored only on clock edges) or asynchronous (immediate) is critical for reset strategies. Given Data / Assumptions: Standard TTL/CMOS D and J–K flip-flops include asynchronous active-low PRESET and CLEAR pins (often labeled PRE, CLR, or direct set/reset). Datasheets typically denote them with independent timing specs and overriding priority. Some specialized synchronous reset/set devices exist but are explicitly labeled and behave differently. Concept / Approach: “Normally” in industry practice, PRESET and CLEAR are asynchronous: when asserted, they immediately force Q to 1 or 0 regardless of the clock, provided input pulse width meets minimum requirements. Synchronous reset/set signals are applied through the data path or synchronous control inputs and only take effect at the active clock edge. Step-by-Step Solution: Examine pin functions: PRE and CLR act without waiting for a clock edge.Asynchronous action overrides D/J/K data inputs.Releasing PRE/CLR returns the device to normal edge-triggered operation.Therefore the statement that they are “normally synchronous” is incorrect. Verification / Alternative check: Datasheet timing diagrams show direct set/reset paths with independent tPHL/tPLH, confirming asynchronous behavior. Why Other Options Are Wrong: “Correct” reverses standard behavior. Technology qualifiers (“only in CMOS”) or RC edge-conditioning do not change the fundamental async nature in common parts. Common Pitfalls: Failing to synchronize asynchronous deassertion can cause metastability; not meeting minimum pulse widths; forgetting active-low polarity. Final Answer: Incorrect

Question 13

Schematic symbols — identifying edge-triggered flip-flops by the clock triangle Determine whether the statement is correct: “Edge-triggered flip-flops can be identified by the triangle on the clock input.”

Accepted Answer

Introduction / Context: Schematic symbols convey triggering style. A triangle at the clock input denotes edge sensitivity; an additional bubble indicates inversion (negative-edge). Recognizing these marks helps read timing intent without a datasheet. Given Data / Assumptions: Triangle on the clock pin = edge-triggered sampling. No triangle (just a gate-like enable) typically indicates level-sensitive latching. Bubble at the clock input denotes active-low (falling-edge) triggering when combined with the triangle. Concept / Approach: Graphic conventions: triangle = edge, bubble = inversion. Thus, a triangle alone usually means positive-edge; triangle plus bubble means negative-edge. Designers rely on these to quickly identify behavior in multi-page schematics. Step-by-Step Solution: Inspect the clock input symbol on the flip-flop.If a triangle is present, it is an edge-triggered device.If a bubble accompanies the triangle, interpret as falling-edge sensitivity.Therefore the statement is correct. Verification / Alternative check: Compare standard symbols in logic family documentation; they consistently use the triangle for edge-triggered flip-flops. Why Other Options Are Wrong: “Incorrect” contradicts standard schematic notation. Requiring a bubble or restricting to J–K types is unnecessary; the convention applies to D, T, and J–K flip-flops. Common Pitfalls: Confusing enable pins on latches (no triangle) with clocks; misreading bubble polarity; assuming edge polarity without checking for the bubble. Final Answer: Correct

Question 14

In sequential logic design, a level-sensitive D-type latch is said to be "transparent" when its ENABLE (or G) control is asserted. Evaluate the statement: "A D-type latch changes state and follows the D input regardless of the ENABLE level." Is this…

Accepted Answer

Introduction / Context: D-type latches are fundamental storage elements used to hold a single bit in many digital systems. They are often used to create temporary storage, to build flip-flops, and to manage timing within pipelines and interface circuits. Understanding when a D latch responds to its input (D) and when it ignores changes is critical for avoiding unintended transparency and race conditions. Given Data / Assumptions: We are discussing a standard level-sensitive D latch (sometimes labeled D latch, Gated D latch, or D latch with ENABLE). The control input is ENABLE (also shown as G or EN). A positive-level latch is transparent when ENABLE = 1; a negative-level latch is transparent when ENABLE = 0. No edge-triggering is implied; this is not a D flip-flop. Concept / Approach: A level-sensitive D latch passes the D input to Q only while ENABLE is in its active level. When ENABLE is inactive, the latch holds (stores) the last value. Thus, the latch does not “follow D regardless of ENABLE.” Instead, the ENABLE strictly gates transparency. Step-by-Step Solution: Identify device: level-sensitive D latch.Define behavior: transparent when ENABLE is active; stores when ENABLE is inactive.Compare to claim: claim says it follows D regardless of ENABLE.Conclude: the claim contradicts the enable-controlled transparency; therefore it is incorrect. Verification / Alternative check: Examine a textbook timing diagram: Q tracks D only during the active level of ENABLE; outside that window, Q remains constant despite D changes. Why Other Options Are Wrong: Correct: Would imply no gating by ENABLE, which is false for latches.Depends on clock polarity only: Latches are level-sensitive, not edge-triggered; polarity matters for which level is active, but “regardless of ENABLE” is still wrong.Insufficient information: Standard latch behavior is well-defined; enough information is present. Common Pitfalls: Confusing level-sensitive latches with edge-triggered flip-flops.Leaving ENABLE active too long, causing unintended transparency and races. Final Answer: Incorrect

Question 15

Consider a negative edge-triggered flip-flop (for example, a D or J-K variant that samples on the falling clock edge). Evaluate the statement: "A negative edge-triggered flip-flop accepts inputs only while the clock is at the LOW level." Is this des…

Accepted Answer

Introduction / Context: Edge-triggered flip-flops are the backbone of synchronous digital systems. They capture input data at discrete instants defined by clock edges, enabling deterministic timing. Misunderstanding when data is sampled can lead to timing violations, metastability, and logic errors. Given Data / Assumptions: The flip-flop is negative edge-triggered, meaning it triggers on the high-to-low transition of the clock. Inputs must satisfy setup and hold time requirements around that transition. Between edges, the internal state does not change due to data variations (ignoring asynchronous controls). Concept / Approach: An edge-triggered device samples around an instant—the active clock edge—not throughout the entire LOW or HIGH level. The statement that it accepts inputs only while the clock is LOW confuses level sensitivity with edge sensitivity. The correct view: the device looks at the inputs at the moment of the falling edge (with setup/hold windows), not continuously during the LOW phase. Step-by-Step Solution: Define negative edge-triggered: sensitive at clock falling edge.Identify sampling window: setup time before edge and hold time after edge.Compare claim: “only when clock is LOW.”Conclude: incorrect; the LOW level interval is not the sampling window for edge-triggered devices. Verification / Alternative check: Review timing diagrams: Q updates at the instant of the falling edge; no level-following during the constant LOW interval. Why Other Options Are Wrong: Correct: Would imply level-driven behavior, which is false.Depends on setup/hold only: Setup/hold define margins, not level-wide acceptance.True for master–slave only: Master–slave also acts edge-equivalent; still not “LOW-only.” Common Pitfalls: Confusing latches (level-sensitive) with flip-flops (edge-triggered).Ignoring setup/hold, leading to intermittent failures. Final Answer: Incorrect

Question 16

Characterize a latch device: Is it accurate to say, "Latches are tristate devices and their stored state normally depends on asynchronous inputs"? Evaluate this statement for standard D, SR, or gated latches.

Accepted Answer

Introduction / Context: Precise terminology matters in digital design. “Latch,” “tristate,” and “asynchronous” each have specific technical meanings. Mixing these concepts leads to confusion when reading datasheets, designing interfaces, or analyzing timing behavior. Given Data / Assumptions: We consider common latches: SR latches, gated D latches, and similar level-sensitive storage elements. “Tristate” refers to outputs that can drive logic 1, logic 0, or a high-impedance (Z) state. “Asynchronous inputs” usually refer to preset/clear pins on flip-flops or latches that override clock/enable. Concept / Approach: A latch is a bistable storage element—by default it has two stable output states (0 or 1). It is not inherently a tristate buffer; tristate behavior requires a separate output-enable structure. While some devices add an OE pin to place the output in high impedance, that is not a defining property of a latch. Furthermore, the latch’s state does not “normally depend on asynchronous inputs.” Standard latches depend on their data/control inputs and act when the ENABLE (or S/R) levels are asserted. Asynchronous preset/clear are optional features that force states regardless of enable, but they are not the normal mechanism determining the stored state. Step-by-Step Solution: Identify defining property: a latch is bistable (two states), not tristate.Control behavior: standard D latches are transparent on active ENABLE; otherwise they hold the last value.Asynchronous pins: optional overrides; not the usual dependency.Therefore, the quoted statement is inaccurate. Verification / Alternative check: Consult typical symbols: latch symbols lack the three-state triangle/OE found on tristate buffers; datasheets list optional asynchronous controls separately. Why Other Options Are Wrong: Correct: Would mischaracterize both tristate and dependency on asynchronous inputs.True only for transparent SR latches: Even SR latches are not intrinsically tristate.Depends on OE pin: While OE can tristate the output, that does not make the latch itself “a tristate device” by definition. Common Pitfalls: Assuming any device with an OE pin is “tristate by nature.”Confusing asynchronous set/clear with normal data capture behavior. Final Answer: Incorrect

Question 17

Parallel data transfer between two separate register banks: Does a parallel transfer require more than one shift pulse, or is it accomplished without shift pulses using a load/enable action?

Accepted Answer

Introduction / Context: Register-to-register data movement is ubiquitous in CPUs, microcontrollers, and digital signal processors. There are two primary paradigms: serial shifting (bit-by-bit over multiple clock pulses) and parallel transfer (all bits simultaneously). Understanding the difference is essential for estimating latency and designing control logic. Given Data / Assumptions: Two distinct register banks are involved (source and destination). “Parallel transfer” means all N bits move concurrently across N data lines. Standard synchronous control signals like LOAD, ENABLE, or WRITE are available. Concept / Approach: In a parallel transfer, data lines carry all bits at once; the destination register captures them in a single action (often one clock, strobe, or load pulse). Shift pulses are associated with serial transfers, where each shift moves data by one position and multiple pulses are needed to move a full word. Step-by-Step Solution: Define serial vs. parallel: serial uses a single data line with shifting; parallel uses multiple lines simultaneously.Evaluate the claim: “Parallel transfer requires more than one shift pulse.”Recognize that shifting is irrelevant to pure parallel transfer.Conclusion: The statement is incorrect; parallel transfer is typically achieved with a single load/enable event, not shift pulses. Verification / Alternative check: Examine timing for PIPO registers: data is applied to D inputs; a single LOAD edge captures the entire word. Why Other Options Are Wrong: Correct: Would imply parallel transfer needs serial-like shifting, which is false.Only true for serial-in/parallel-out: That case is serial loading; the prompt is about parallel between registers.Depends on the number of bits: Bit width does not change the parallel capture mechanism. Common Pitfalls: Confusing bus-wide parallel moves with shift-register operations.Overlooking required control strobes (LOAD/WRITE) for proper capture. Final Answer: Incorrect

Question 18

Role of the J–K flip-flop in synchronous design: Is it accurate to state that the J–K flip-flop is a standard primitive building block for clocked (sequential) logic, widely used in textbooks and libraries?

Accepted Answer

Introduction / Context: Flip-flops form the foundation of synchronous sequential circuits. Among the common types are SR, J–K, T, and D flip-flops. The J–K flip-flop is historically significant and remains conceptually important due to its versatile input behavior and ability to toggle, set, or reset under clock control. Given Data / Assumptions: The term “standard primitive” refers to a basic, canonical building block used in teaching and design libraries. We are considering synchronous (clocked) logic circuits. We ignore vendor-specific HDL primitives and focus on general digital design concepts. Concept / Approach: The J–K flip-flop extends the SR flip-flop by resolving the invalid input condition (S = R = 1). With J = K = 1, the device toggles on the active clock edge, making it convenient for counters and state machines. Many textbooks present J–K, D, and T flip-flops as core primitives; although modern HDL synthesis often maps everything to D flip-flops internally, the J–K remains a recognized primitive in theory and some libraries. Step-by-Step Solution: Identify primitive role: J–K provides set (J=1,K=0), reset (J=0,K=1), hold (J=0,K=0), and toggle (J=1,K=1).Clocked operation: state changes only on the specified clock edge (with setup/hold observed).Use cases: counters, divide-by-two stages, configurable state machines.Conclusion: J–K is indeed a standard primitive in synchronous design pedagogy and practice. Verification / Alternative check: Cross-check learning resources: most include J–K flip-flops alongside D and T as core devices. Why Other Options Are Wrong: Incorrect: Denies widely accepted classification.Only true for asynchronous logic: J–K is clocked; asynchronous refers to preset/clear, not its main operation.Only true for CPLD devices: The concept is technology-agnostic. Common Pitfalls: Confusing “primitive” with “most commonly synthesized form” (D FF). Tools often infer D FFs even when behavior is written as J–K. Final Answer: Correct

Question 19

Construction insight: Can a D flip-flop be formed by simply inserting an inverter between the SET input and the clock terminal? Evaluate this claim relative to standard D flip-flop implementations from latches or J–K equivalents.

Accepted Answer

Introduction / Context: Understanding how different flip-flops relate helps when converting between primitives or when a required type is unavailable. A D flip-flop can be constructed from lower-level elements, but the relationships must preserve synchronous behavior and proper control of set/reset paths. Given Data / Assumptions: SET and CLEAR are asynchronous override inputs on many flip-flops. The clock input governs synchronous sampling of the data path. The claim suggests adding an inverter between SET and CLOCK to create a D flip-flop. Concept / Approach: A valid construction routes combinational logic so that the synchronous data path implements Q(next) = D at the active clock edge. Typical conversions include: building a D flip-flop from a pair of level-sensitive D latches (master–slave) or from a J–K by wiring J = D and K = D’ (complement). Inserting an inverter between SET and CLOCK does not create a proper synchronous data path; it misuses an asynchronous control and risks forcing states independent of clocking, violating setup/hold timing and the intended function. Step-by-Step Solution: State valid method: D FF = master latch + slave latch with opposite level enables.Alternative: From J–K, wire J = D and K = D’ to realize D behavior on the clock edge.Evaluate the claim: SET is asynchronous; inverting it into CLOCK path does not synthesize D behavior.Conclude: the statement is incorrect. Verification / Alternative check: Simulate timing: any change on SET immediately overrides Q, independent of clock edge; this is not a D flip-flop. Why Other Options Are Wrong: Correct / True only with SR core / Depends on clear: None repair the fundamental misuse of asynchronous controls. Common Pitfalls: Confusing asynchronous preset/clear with synchronous data inputs.Ignoring the two-latch (master–slave) structure that enforces edge behavior. Final Answer: Incorrect

Question 20

Behavior of the J–K flip-flop at J = 1 and K = 1: Does the J–K flip-flop remove the SR “invalid” condition by toggling the stored state on the active clock transition when both inputs are HIGH?

Accepted Answer

Introduction / Context: The SR flip-flop suffers from an invalid state when S = 1 and R = 1 simultaneously. The J–K flip-flop was developed to overcome this limitation while retaining set, reset, and hold behaviors. One hallmark of the J–K device is its “toggle” action when both inputs are asserted together at the clock edge. Given Data / Assumptions: A clocked J–K flip-flop is considered (edge-triggered or master–slave equivalent). Inputs J and K are both HIGH (logic 1) during the valid setup/hold window around the active clock edge. No asynchronous preset/clear is active. Concept / Approach: The truth behavior of a J–K flip-flop includes: J = 0, K = 0 → hold; J = 1, K = 0 → set; J = 0, K = 1 → reset; J = 1, K = 1 → toggle (Q(next) = Q’(current)). This elegantly resolves the SR invalid combination by defining a deterministic response—state inversion—on the clock transition. Step-by-Step Solution: Assume Q(current) = 0; with J = 1 and K = 1 at the edge → Q(next) = 1.Assume Q(current) = 1; with J = 1 and K = 1 at the edge → Q(next) = 0.Thus, each qualifying clock edge flips the stored bit, realizing a divide-by-two stage when driven continuously.This behavior is independent of edge polarity (positive or negative), provided timing requirements are met. Verification / Alternative check: Configure J = K = 1 and clock at frequency f; the Q output toggles at f/2, confirming the toggle rule. Why Other Options Are Wrong: Incorrect: Denies a defining property of the J–K flip-flop.Only true for positive-edge devices: Toggle applies to either edge polarity devices; the edge type only sets the sampling instant.Only when asynchronous clear is asserted: Asynchronous clear forces reset, not toggle. Common Pitfalls: Violating setup/hold for J and K, which can prevent reliable toggling.Assuming toggle during level intervals; toggle occurs at the active edge only. Final Answer: Correct

Flip-Flops Questions