Question 1

Digital storage concept — D latch fundamentals: A D (data) latch is a level-sensitive storage element that propagates the value present on its data input only while its enable/control input is active. In standard form, a D latch has a single data-in…

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Introduction / Context: A D (data) latch is a level-sensitive storage element used to hold a single-bit value. It is commonly introduced before edge-triggered flip-flops to explain basic storage behavior, transparency when enabled, and isolation when disabled. This item checks whether you recognize the number and role of its inputs. Given Data / Assumptions: Standard D latch symbol with one labeled D input. An enable (EN, G, or C) input that controls transparency. Outputs Q and Q̄ are complementary. No preset/clear pins are assumed unless explicitly stated. Concept / Approach: The D latch is built so that only a single data path drives the internal cross-coupled gates: the D input. The enable input is not a data input; it is a control line. When EN is active, Q follows D (transparent). When EN is inactive, Q holds its last value. Therefore, “one data-input line” means exactly one signal carries the information to be stored: D. Step-by-Step Solution: Identify functional inputs: D (data) and EN (control).Classify EN as control because it gates, but does not itself encode the bit value.Confirm that stored information originates from D alone.Conclude that the statement is correct. Verification / Alternative check: Inspect truth behavior: with EN = 1, Q := D; with EN = 0, Q := previous Q. Only D determines the stored bit when sampling occurs; EN merely permits or blocks the transfer. Why Other Options Are Wrong: Incorrect: A second “data” input does not exist; EN is control, not data. Depends on clock edge polarity: Latches are level-sensitive, not edge-triggered. Undefined for transparent devices: Operation is well-defined under enable control. Only true for master–slave flip-flops: Master–slave is a flip-flop structure, not a simple latch. Common Pitfalls: Confusing EN with an additional data channel; mixing up latches (level-sensitive) and flip-flops (edge-triggered); assuming preset/clear exist by default in all symbols. Final Answer: Correct

Question 2

74xx logic device behavior — 7474 input types: The 7474 is a dual D-type positive-edge-triggered flip-flop. It presents two distinct classes of inputs: synchronous inputs (D, CLK) that act on the active clock edge, and asynchronous inputs (PRE, CLR)…

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Introduction / Context: The 7474 is a classic TTL dual D-type flip-flop used widely in introductory and intermediate digital design. Understanding which pins are synchronous (sampled on clock edge) versus asynchronous (override regardless of clock) is essential for reliable reset/initialize logic and timing analysis. Given Data / Assumptions: Device: 7474 dual D-type edge-triggered flip-flop. Synchronous inputs: D, CLK (state update occurs on clock edge). Asynchronous inputs: PRE (preset) and CLR (clear), typically active-low. Positive-edge triggering unless otherwise specified by variant. Concept / Approach: State changes from the data path occur only at the designated clock edge (synchronous). However, preset and clear are designed to force Q to 1 (PRE) or 0 (CLR) at any time they are asserted (asynchronous), independent of D or the clock. This division is explicit in datasheets and timing diagrams. Step-by-Step Solution: Identify synchronous signals: D and CLK operate on the clock edge.Identify asynchronous signals: PRE and CLR override stored state immediately.Confirm that both types coexist on 7474 packages.Conclude statement is correct. Verification / Alternative check: Examine timing: asynchronous inputs show no setup/hold relative to clock for their primary function, while D requires setup/hold around the active edge. This difference verifies two classes of inputs. Why Other Options Are Wrong: Incorrect / Only asynchronous: Contradicted by edge-triggered data path. Behavior depends on supply voltage only: Power affects limits, not input class. Applies only to latches: The 7474 is a flip-flop, not a level-sensitive latch. Common Pitfalls: Driving PRE and CLR simultaneously; forgetting they are usually active-low; violating D setup/hold and mislabeling timing problems as asynchronous faults. Final Answer: Correct

Question 3

Gated S–R storage element classification: A gated S–R latch responds to its inputs only while the enable (gate) is asserted; this level-controlled behavior is considered synchronous (with respect to the gate level), not purely asynchronous. Judge th…

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Introduction / Context: Storage elements fall into two broad categories: level-sensitive latches and edge-triggered flip-flops. The term “asynchronous” usually refers to inputs that change state without reference to a clock or enable, while “synchronous” means state changes occur under control of a timing signal (clock or enable). Given Data / Assumptions: A gated S–R latch has S and R inputs plus an enable (EN) signal. While EN is active, the latch follows S/R; when EN is inactive, it stores. No edge-trigger mechanism is present; it is level-controlled. Concept / Approach: Because the gated latch admits state changes only when EN is asserted, it is synchronized to the enable level. Although not edge-triggered, it is not “asynchronous” in the sense of acting at any time; it is synchronous to EN. Asynchronous actions would occur regardless of any controlling timing signal (e.g., preset/clear overriding a flip-flop at any time). Step-by-Step Solution: Classify uncontrolled inputs as asynchronous; controlled-by-EN inputs as synchronous.Observe that S/R affect state only when EN = active.Therefore, the gated S–R latch is synchronous with respect to EN.Conclude the statement “is asynchronous” is incorrect. Verification / Alternative check: Timing diagrams show Q reacting to S/R only during active EN intervals; outside those intervals, Q holds, which is textbook synchronous (level-based) behavior, not free-running asynchronous change. Why Other Options Are Wrong: Correct: Contradicts level-controlled nature. NAND-based or using Q̄: Gate technology or which output is observed does not alter the synchronous gating concept. Depends on propagation delay: Delays affect timing margins, not classification. Common Pitfalls: Equating “not edge-triggered” with “asynchronous”; ignoring enable gating; forgetting that “asynchronous inputs” refers to PRE/CLR-type overrides. Final Answer: Incorrect

Question 4

Design intuition — building an S–R flip-flop (latch) from basic gates: Given the cross-coupled NOR or NAND structures introduced earlier in digital logic, designing a basic S–R latch is a straightforward exercise in feedback and mutual exclusion. Ev…

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Introduction / Context: The S–R latch (often called an S–R “flip-flop” informally) is the canonical memory element built from two cross-coupled gates. It is typically one of the first sequential circuits students design after learning basic logic gates and feedback principles. Given Data / Assumptions: Cross-coupled NOR produces active-HIGH S and R inputs. Cross-coupled NAND produces active-LOW inputs. Design goal is a bistable memory with set and reset control. No metastability-proofing or clocking is required for the basic latch exercise. Concept / Approach: The design hinges on mutual reinforcement through feedback: one gate output feeds the other’s input. Applying S forces Q = 1 (set), applying R forces Q = 0 (reset), and releasing both maintains the state through cross-coupling. The schematic is small, symmetrical, and teaches hazards such as the invalid input combination for the chosen technology (NOR: S = R = 1; NAND: S̄ = R̄ = 0). Step-by-Step Solution: Choose gate family (NOR for active-HIGH or NAND for active-LOW control).Cross-couple outputs to the opposite gate’s input to create positive feedback.Label control inputs S and R and outputs Q and Q̄.Verify truth behavior: set, reset, and hold (with forbidden case). Verification / Alternative check: Simulate with two gates; observe bistability and proper response. Minimal gate count and symmetry confirm design simplicity for instructional purposes. Why Other Options Are Wrong: Incorrect: The basic S–R latch is among the simplest sequential circuits. Only for edge-triggered versions: Edge-triggered flip-flops are more complex; the latch is simpler. Only with transmission gates: Transmission gates are for CMOS latch/FF implementations, not required for the conceptual design. Depends exclusively on fan-out: Fan-out matters later; not core to topology simplicity. Common Pitfalls: Overlooking the invalid input case; confusing latch vs flip-flop terminology; forgetting active-level conventions between NOR and NAND implementations. Final Answer: Correct

Question 5

Power-up behavior of flip-flops: When power is first applied to a sequential circuit, a flip-flop’s initial state is not guaranteed unless specific initialization (reset or preset) circuitry is provided. Assess the statement: “A flip-flop’s normal s…

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Introduction / Context: Real-world sequential circuits must consider power-up behavior. Without deterministic initialization, storage elements can power up in either state due to device mismatch, leakage, and noise, leading to unpredictable system behavior. Given Data / Assumptions: Generic flip-flops (D, JK, T) without guaranteed power-on reset. No explicit reset (CLR) or preset (PRE) asserted at power-up. Normal device variations and metastability possibilities. Concept / Approach: Absent a designed initialization path, startup state is indeterminate. Designers add RC reset networks, dedicated POR (power-on reset) ICs, or assert asynchronous CLR/PRE to force known states. Therefore, claiming the state is “always SET” is incorrect; it may be set, reset, or metastable before settling. Step-by-Step Solution: Consider two symmetrical storage nodes with slight mismatch at power-up.Random offsets and noise push the latch into one stable state.Without controlled reset, either Q=1 or Q=0 may result.Hence the statement “always SET” does not hold. Verification / Alternative check: Examine datasheets: many specify “undefined at power-up” and recommend external reset. Simulation with uninitialized nodes also shows indeterminate initial state until forced. Why Other Options Are Wrong: Correct: Contradicted by standard initialization practices. True only for JK flip-flops / Schmitt triggers: Device type or input conditioning does not guarantee SET on power-up. Depends solely on load capacitance: Capacitance influences behavior but does not ensure a fixed starting state. Common Pitfalls: Assuming symmetric devices pick a consistent state; forgetting POR requirements; relying on simulation defaults that silently initialize to zeros or ones. Final Answer: Incorrect

Question 6

Triggering modes in multivibrators: Multivibrators (astable, monostable, and bistable) can be free-running, edge-triggered, or level-triggered depending on configuration. Evaluate the claim: “Multivibrators must be level-triggered.”

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Introduction / Context: Multivibrators form the foundation of timing circuits. Their operating modes include astable (oscillators), monostable (one-shot), and bistable (flip-flop). Triggering characteristics differ by design, not by an absolute rule requiring level triggering. Given Data / Assumptions: Astable: self-oscillating, no trigger required. Monostable: typically edge-triggered to produce a fixed pulse. Bistable: toggled by level or edge, depending on implementation. Concept / Approach: Claiming “must be level-triggered” is incorrect because many monostable designs deliberately use edge triggering to avoid pulse-width sensitivity on the trigger input. Astables need no external trigger at all, while bistables may respond to either edges or levels depending on circuitry (e.g., debounced pushbuttons feeding edge detectors). Step-by-Step Solution: Identify multivibrator type and its typical trigger mechanism.Note that monostables often require a rising/falling edge to start timing.Recognize that astables are free-running; no trigger mode applies.Therefore, a blanket “must be level-triggered” statement is false. Verification / Alternative check: Check 555 monostable datasheets: triggering is by a threshold edge crossing, not a static level duration (beyond minimum pulse width). Why Other Options Are Wrong: Correct: Conflicts with standard monostable and astable operation. True only for astable/CMOS/50% duty: These constraints do not impose level triggering. Common Pitfalls: Assuming “trigger” always means a sustained level; ignoring edge-detection networks; overlooking that different multivibrator types behave differently. Final Answer: Incorrect

Question 7

Synchronous vs. asynchronous logic — classification check: Simple gate networks (pure combinational logic) have no clocked storage and thus are asynchronous; transparent S–R latches are level-sensitive, not edge-synchronous. Evaluate the statement: …

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Introduction / Context: In digital design, “synchronous” implies that state changes happen in lockstep with a timing reference (usually a clock edge). Combinational circuits lack memory and do not synchronize to a clock, and transparent latches follow inputs while enabled rather than at discrete edges. Given Data / Assumptions: Simple gate circuits: no storage, purely input-driven. Combinational logic: outputs are functions of current inputs only. Transparent S–R latch: level-sensitive; follows inputs during enable. Concept / Approach: Because combinational logic has no concept of “state update on a clock,” it is asynchronous. Transparent latches change state whenever the enable is active (level), not strictly at a clock edge. Hence calling all of these “synchronous” is incorrect in the conventional clocked-systems sense. Step-by-Step Solution: Classify combinational networks as asynchronous (no clocked memory).Classify transparent latches as level-controlled, not edge-synchronous.Reserve “synchronous” primarily for edge-triggered flip-flop systems or level-gated systems treated as synchronous only within controlled intervals.Therefore, the global statement is false. Verification / Alternative check: Timing analysis: combinational propagation delays exist without reference to a clock; latches require careful enable timing to avoid transparency hazards, reinforcing they are not purely edge-synchronous. Why Other Options Are Wrong: Correct: Contradicted by definitions. “Only synchronous when gated by RC” or “fan-in limited to 2” or “Schmitt-trigger gates”: These conditions do not change the fundamental classification. Common Pitfalls: Equating “has timing” with “is synchronous”; ignoring the difference between level gating and edge triggering; overlooking that combinational logic has no internal state to synchronize. Final Answer: Incorrect

Question 8

555 timer operating modes: The popular 555 timer integrated circuit can be configured in multiple modes. In basic usage, it supports astable (free-running oscillator) and monostable (one-shot) operation with simple external components. Judge the sta…

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Introduction / Context: The 555 timer is a staple of timing and waveform-generation circuits. Its internal comparators, flip-flop, and discharge transistor allow flexible configurations with just resistors and capacitors, making it ideal for lab and product prototyping. Given Data / Assumptions: Standard bipolar or CMOS 555 timer. External R, C components define timing. Common configurations: astable and monostable (and also bistable with suitable wiring). Concept / Approach: In astable mode, the 555 charges and discharges the capacitor between threshold levels, producing a continuous square/rectangular wave. In monostable mode, a trigger edge initiates a single pulse of defined width, after which the output returns to its stable state. Both configurations are documented and widely used. Step-by-Step Solution: Astable: connect two resistors and one capacitor; output oscillates continuously.Monostable: use one resistor and capacitor; a trigger creates a pulse of width T ≈ 1.1 * R * C.Verify that no microcontroller is needed; operation is analog/digital hybrid.Conclude the statement is correct. Verification / Alternative check: Reference application notes: both modes are standard, with equations for frequency, duty cycle, and pulse width based on R and C values. Why Other Options Are Wrong: Incorrect / Only astable / Only monostable: Contradict numerous canonical application circuits. Requires external microcontroller: Not required; 555 is self-contained with passive components. Common Pitfalls: Forgetting trigger polarity in monostable mode; ignoring reset pin behavior; miscalculating duty cycle in astable without diode steering for duty correction. Final Answer: Correct

Question 9

Meaning of CLEAR/RESET in flip-flops: By definition, asserting CLEAR or RESET drives the primary output Q to logic 0. Evaluate the statement: “The Q output of a flip-flop is normally HIGH when the device is in the CLEAR or RESET state.”

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Introduction / Context: Asynchronous control inputs on flip-flops are labeled PRE (preset) and CLR (clear) or SET and RESET depending on convention. Their purpose is to force the output to a known state for initialization or control. Given Data / Assumptions: CLR/RESET forces Q = 0 by definition. PRE/SET forces Q = 1 by definition. Active levels (low or high) depend on device family but the logical effect is consistent. Concept / Approach: If a device is said to be in “CLEAR” or “RESET,” its Q output is driven to 0. Therefore, the statement claiming Q is HIGH during CLEAR/RESET is backwards. Only PRE/SET produces Q = 1. Confusion often arises from active-low pin naming (e.g., CLR̄), but the functional outcome at Q is unambiguous. Step-by-Step Solution: Map control names to outcomes: CLEAR/RESET → Q = 0; PRE/SET → Q = 1.Check device truth table for active-low vs active-high pins.Verify that the effect on Q does not depend on edge polarity of the clock.Conclude the statement is incorrect. Verification / Alternative check: Consult typical 7474 or 74HC74 tables: CLR̄ asserted low drives Q = 0 immediately, proving the point. Why Other Options Are Wrong: Correct: Opposite of defined behavior. NAND-based / negative-edge / supply ramp rate: Implementation details and clocking do not invert the meaning of CLEAR/RESET. Common Pitfalls: Mixing up active-low pin assertions; confusing PRE/SET with CLR/RESET; assuming clock is required for asynchronous actions (it is not). Final Answer: Incorrect

Question 10

Validity of S–R latch input combinations: A basic S–R latch has a forbidden or invalid input combination (depending on NOR or NAND implementation). Assess the claim: “The S–R flip-flop has no invalid or unused state.”

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Introduction / Context: The S–R latch is the quintessential bistable made from cross-coupled NOR or NAND gates. While simple, it includes a prohibited input combination that leads to ambiguity or both outputs at the same level, violating complementarity. Given Data / Assumptions: NOR-based S–R (active-high): S=1 and R=1 is invalid. NAND-based S̄–R̄ (active-low): S̄=0 and R̄=0 is invalid. Outputs Q and Q̄ should be complements in valid operation. Concept / Approach: In the forbidden case, both cross-coupled gates are forced into the same driven state. When inputs are released, final state can be unpredictable and may depend on tiny device mismatches, breaking determinism. Therefore, stating that there is “no invalid or unused state” is factually wrong. Step-by-Step Solution: Identify technology: NOR or NAND implementation.List valid control combinations (set, reset, hold).Highlight the forbidden input: NOR (1,1) or NAND (0,0).Explain that this leads to non-deterministic release and broken complementarity. Verification / Alternative check: Truth/characteristic tables in textbooks mark the forbidden row explicitly (often with an X). Simulators also flag undefined behavior when both controlling inputs are asserted concurrently in these structures. Why Other Options Are Wrong: Correct: Contradicted by standard tables. “Valid only for edge-triggered” or “if outputs are not complemented”: Edge triggering and labeling do not eliminate the forbidden combination. Temperature: Environmental factors do not turn an invalid input into a valid one. Common Pitfalls: Driving both inputs active “just to be safe”; failing to add gating to prevent overlap; misunderstanding active-high vs active-low conventions and thereby asserting the wrong pair simultaneously. Final Answer: Incorrect

Question 11

Monostable (one-shot) multivibrator concept: A one-shot circuit is also known as a timer because a trigger produces a single pulse of defined width. Evaluate the statement.

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Introduction / Context: A one-shot, formally called a monostable multivibrator, is fundamental in digital timing. When triggered, it produces one output pulse whose width is set by external components or internal timing, so many practitioners casually call it a timer. This question asks you to judge that naming and understand why it is reasonable. Given Data / Assumptions: A one-shot (monostable) has one stable state and one quasi-stable state. On a trigger edge, the output moves to the quasi-stable state for a defined duration (pulse width), then returns to the stable state. Timing is set by RC components or internal references in IC one-shots. Concept / Approach: The essence of a timer is to create a time interval. A one-shot does exactly that on demand: it generates a pulse with width t_w determined by design parameters (e.g., t_w = k * R * C for many devices). That pulse can debounce inputs, stretch narrow edges, create delays, or gate logic for a known time. Step-by-Step Solution: Recognize that “timer” describes a function, not necessarily a specific topology.A monostable generates a single, timed output pulse when triggered.This timed behavior is used to implement delays, pulse stretching, and interval generation.Therefore, calling a one-shot a “timer” is appropriate in context. Verification / Alternative check: Datasheets for classic one-shot ICs (e.g., 74121/74123/4538) specify equations for pulse width vs. R and C, underscoring the timing role. Why Other Options Are Wrong: Incorrect: Contradicts the clear timing behavior of one-shots.Only true for astable circuits: Astable oscillators self-run; a one-shot is trigger-driven.Only true for bistable latches: Bistables hold states; they do not generate timed pulses. Common Pitfalls: Confusing monostable (one-shot) with astable (free-running clock) or bistable (flip-flop/latch). Assuming “timer” means only a 555-type oscillator; it also covers triggered timing intervals. Final Answer: Correct

Question 12

Flip-flop timing behavior: Generally, the hold time is short enough that the flip-flop output assumes the state dictated by synchronous control inputs just prior to the active clock edge. Evaluate the statement.

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Introduction / Context: Flip-flops sample synchronous inputs (D, J/K, T with enables) around an active clock transition. Two key timing specs guarantee correct sampling: setup time and hold time. This item checks your understanding of how short hold time supports correct state capture. Given Data / Assumptions: Synchronous inputs satisfy setup time (stable before clock edge). Hold time is small but nonzero (must remain stable briefly after the edge). Active edge could be rising or falling, depending on the device. Concept / Approach: If inputs meet setup and hold, the device samples reliably at the active edge and the output transitions to the state commanded by those inputs. Many modern flip-flops specify minimal or even zero hold time thanks to internal clocking schemes, which aligns with the statement’s “generally short enough.” Step-by-Step Solution: Ensure synchronous inputs are valid and stable for at least t_setup before the active edge.Maintain inputs stable for at least t_hold after the edge.Given small t_hold, the output resolves to the state defined immediately prior to the edge.Therefore, the statement is correct under standard timing practice. Verification / Alternative check: Consult device timing diagrams: the sampling instant is at the active edge, and output changes after t_co (clock-to-output delay) when setup/hold are met. Why Other Options Are Wrong: Incorrect: Conflicts with basic edge-triggered sampling behavior.True only for asynchronous inputs: Asynchronous inputs are not governed by setup/hold in the same way and can violate metastability rules.True only for negative-edge devices: Applies to either edge; polarity is irrelevant. Common Pitfalls: Ignoring hold time because it is “small”; changing inputs right at the edge; mixing asynchronous set/reset with synchronous data timing. Final Answer: Correct

Question 13

Flip-flop input classes: Inputs that cause the flip-flop output to change immediately, independent of the clock (for example, asynchronous set or reset), are called asynchronous. Evaluate the statement.

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Introduction / Context: Flip-flops may accept two categories of control: synchronous (sampled by the clock) and asynchronous (override the state regardless of the clock). Recognizing the difference is central to safe design and timing closure. Given Data / Assumptions: Typical asynchronous pins: preset (set) and clear (reset). These pins dominate the internal state forcing Q = 1 or Q = 0. They are not qualified by the clock and can act at any time. Concept / Approach: Asynchronous control immediately forces the state; therefore, it must be deasserted synchronously (or safely) to avoid recovery/removal violations. Synchronous controls (like D, J/K) affect the state only on the active clock edge. Step-by-Step Solution: Identify inputs that bypass the clock (preset/clear).Note they act immediately (subject to propagation delay), not at the edge.Hence, by definition, these are asynchronous inputs.Therefore, the statement is correct. Verification / Alternative check: Datasheets label these pins as asynchronous and specify recovery/removal times rather than setup/hold. Why Other Options Are Wrong: Incorrect: Contradicts how preset/clear operate.Only true for latches or only for positive-edge: Asynchronicity is independent of clocking style or edge polarity. Common Pitfalls: Asserting asynchronous signals near a clock edge without meeting recovery/removal; leaving async pins floating; assuming they are sampled by the clock. Final Answer: Correct

Question 14

NOR-gate S–R latch reasoning: For a NOR-based S–R flip-flop (latch), if the outputs are Q = 1 and Q̄ = 0 (the set state), what are the input levels S and R?

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Introduction / Context: The classic S–R latch built from cross-coupled NOR gates has two control inputs: Set (S) and Reset (R). Understanding the correspondence between input assertions and output states is essential for correct design and debugging. Given Data / Assumptions: NOR-based S–R latch (active-high S and R). Outputs: Q and Q̄ are complements in valid states. We are given Q = 1 and Q̄ = 0, i.e., the set state. Concept / Approach: For NOR-gate implementation, an asserted input is logic 1. Driving S = 1 forces Q = 1 regardless of feedback, provided R = 0. Conversely, R = 1 forces Q = 0. With both low (S = 0, R = 0), the latch holds its previous state. S = R = 1 is invalid for a NOR latch. Step-by-Step Solution: Desired outputs: Q = 1, Q̄ = 0.To set Q = 1 in a NOR latch, assert S = 1 while keeping R = 0.After the set action, S can be returned to 0 to hold the state.Therefore, the appropriate input combination is S = 1, R = 0. Verification / Alternative check: Truth summary: S,R = 1,0 → set; 0,1 → reset; 0,0 → hold; 1,1 → invalid. The given outputs correspond to the set line asserted. Why Other Options Are Wrong: S = 0, R = 1: This would reset, making Q = 0.S = 0, R = 0: Hold previous state; does not guarantee Q = 1.S = 1, R = 1: Invalid for a NOR S–R latch (both outputs forced low initially). Common Pitfalls: Confusing NOR- and NAND-based latch conventions; forgetting that S = R = 1 (NOR) is invalid; assuming hold rather than considering the need to assert S to set. Final Answer: S = 1, R = 0

Question 15

Flip-flop state validity: Some flip-flop configurations include input combinations that result in invalid or forbidden states. Evaluate the statement.

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Introduction / Context: Not all flip-flop input combinations produce defined, stable outputs. Classic S–R latches built with NOR or NAND gates are well-known examples. Recognizing these forbidden states prevents unreliable behavior and design errors. Given Data / Assumptions: NOR-based S–R: S = 1 and R = 1 is invalid. NAND-based S–R: S = 0 and R = 0 is invalid. Other types (JK, D, T) avoid many invalid states via internal gating but still have asynchronous constraints. Concept / Approach: An invalid state arises when both outputs are forced to the same value or when the cross-coupled feedback cannot settle deterministically. Designers prevent these combinations via input conditioning or by choosing flip-flop types that internally guard against them (e.g., JK instead of simple S–R). Step-by-Step Solution: Consider the NOR S–R latch: S=R=1 forces both NOR outputs to 0, breaking complementarity.When inputs return low simultaneously, the final state depends on tiny skews, leading to unpredictability.Therefore, such input combinations are declared invalid/forbidden.Hence the statement is correct: some flip-flops have invalid input states. Verification / Alternative check: Standard truth tables for S–R latches explicitly mark these cases as invalid or forbidden. Why Other Options Are Wrong: Incorrect: Ignores well-documented forbidden conditions.True only for JK or only for D: Incorrect; the classical examples are basic S–R latches. Common Pitfalls: Driving both S and R active; assuming outputs remain complementary under invalid inputs; not deglitching asynchronous sources that might momentarily assert both inputs. Final Answer: Correct

Question 16

Edge-triggering polarity: A positive edge-triggered flip-flop changes state on a HIGH-to-LOW clock transition. Evaluate the statement.

Accepted Answer

Introduction / Context: Edge-triggered devices respond on a specific transition of the clock: positive (rising) or negative (falling). Understanding clock polarity is essential for timing design and multi-stage pipelines. Given Data / Assumptions: Positive edge-triggered means action on LOW-to-HIGH transition. Negative edge-triggered means action on HIGH-to-LOW transition. Clock-to-output delay follows the triggering edge. Concept / Approach: The statement claims a positive edge-triggered device reacts on a falling edge (HIGH-to-LOW), which contradicts the definition. Therefore, the statement must be judged incorrect. Step-by-Step Solution: Recall: Positive edge = rising edge = LOW-to-HIGH.Given statement: “changes on HIGH-to-LOW.” That is a falling edge.Thus, the statement mislabels the triggering edge.Conclusion: The statement is incorrect. Verification / Alternative check: Datasheets use a triangle or up-arrow symbol near the clock for positive edge; a down-arrow for negative edge. Rising edges are explicitly indicated as 0→1 transitions. Why Other Options Are Wrong: Correct: Would agree with the false claim; not acceptable.“True only for master–slave” or “with Schmitt clocks”: Edge polarity is independent of these details. Common Pitfalls: Confusing edge polarity; overlooking that duty cycle does not affect which edge triggers (only timing margins do). Final Answer: Incorrect

Question 17

Capabilities of digital ICs: Integrated circuits (ICs) can perform sequential operations such as counting and data shifting. Evaluate the statement.

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Introduction / Context: Sequential logic relies on memory elements and clocks to implement operations that depend on past states. Many standard ICs integrate these functions, enabling counters, shift registers, and finite state machines. Given Data / Assumptions: Sequential operations require storage (flip-flops/latches) and combinational logic. Common IC families include counters (e.g., ripple/synchronous) and shift registers (serial-in/serial-out, parallel variants). Clocks and enables control the sequencing. Concept / Approach: ICs like the 74xx/40xx families provide ready-made sequential building blocks. With clocked flip-flops internally, they implement counting (divide-by-N), shifting (data movement and serialization), and more complex behaviors, often with clear timing specs. Step-by-Step Solution: Identify sequential primitives (flip-flops) within ICs.Counters combine flip-flops and logic to increment/decrement states.Shift registers chain flip-flops to move data with each clock.Therefore, ICs do perform counting and shifting. Verification / Alternative check: Reference standard parts: 7490/74HC590 counters; 74HC164/74HC595 shift registers; microcontrollers integrate extensive sequential subsystems. Why Other Options Are Wrong: Incorrect: Contradicts widespread standard devices.Only true for analog ICs or only for programmable logic: Both false; fixed-function digital ICs also perform these operations. Common Pitfalls: Assuming only CPUs can perform sequential tasks; ignoring propagation delays and setup/hold in cascaded sequential stages. Final Answer: Correct

Question 18

Frequency division with toggle flip-flops: “It takes four flip-flops to build a divide-by-4 frequency divider.” Evaluate the statement.

Accepted Answer

Introduction / Context: Frequency division chains are commonly made from toggle (T) flip-flops or JK/D flip-flops configured to toggle. Each stage divides the input frequency by 2. Understanding how many stages are required for a given divide ratio is fundamental. Given Data / Assumptions: Each toggling flip-flop divides frequency by 2. Divide ratio of a cascade equals the product of stage ratios. No special gating or modulus changes are used. Concept / Approach: To obtain divide-by-4, use 2 cascaded flip-flops: 2 * 2 = 4. Four flip-flops would yield divide-by-16, which is excessive for the stated goal. Therefore, the claim that it “takes four” is incorrect. Step-by-Step Solution: Stage 1: f_out1 = f_in / 2.Stage 2: f_out2 = f_out1 / 2 = f_in / 4.Thus only 2 flip-flops are needed for divide-by-4.Four flip-flops → f_in / 16 (divide-by-16), not /4. Verification / Alternative check: Build a small timing diagram for two cascaded T flip-flops; count edges to confirm the 4:1 ratio. Why Other Options Are Wrong: Correct: Would imply four stages are required; false.True only with JK or only with asynchronous clocks: Irrelevant; the divide-by-2 per stage holds for toggling stages regardless of style. Common Pitfalls: Confusing modulus with number of stages; assuming more stages are always needed; overlooking synchronous vs. ripple timing differences which affect phase/skew, not the divide ratio. Final Answer: Incorrect

Question 19

Terminology for oscillators: An astable multivibrator is sometimes referred to as a clock because it free-runs and produces a continuous train of pulses. Evaluate the statement.

Accepted Answer

Introduction / Context: Many digital systems need a periodic timing reference. An astable multivibrator, whether discrete or IC-based, generates a continuous sequence of pulses without external triggering and is frequently used as a simple clock source. Given Data / Assumptions: Astable = no stable state; the circuit oscillates continuously. Output is a periodic waveform (square/rectangular) suitable for driving counters and flip-flops (with level/edge conditioning as needed). Frequency determined by component values or internal timing cells. Concept / Approach: Because it generates pulses at a set frequency, an astable multivibrator serves as a clock for simple applications. More precise systems may use crystal oscillators, PLLs, or clock generator ICs, but the terminology of “clock” for an astable source is common and practical. Step-by-Step Solution: Recognize that a “clock” is any periodic timing reference.Astable circuits provide a self-sustaining periodic output.Therefore, an astable multivibrator can function as, and be called, a clock.Hence, the statement is correct. Verification / Alternative check: Classic 555 in astable mode, or two-inverter RC oscillators, are routinely described as clocks in educational and hobbyist circuits. Why Other Options Are Wrong: Incorrect: Ignores the defining oscillatory behavior of astable circuits.True only for crystals or monostables: A monostable is trigger-based (not a clock), and crystals are a subset; astables broadly qualify. Common Pitfalls: Assuming “clock” requires crystal accuracy; neglecting buffering/shaping needed to meet logic-level specs for different families. Final Answer: Correct

Question 20

Device identification in the 74xx family: The 7476 and 74LS76 are both dual J–K flip-flop integrated circuits (same function, different subfamily). Evaluate the statement.

Accepted Answer

Introduction / Context: The 74xx TTL family includes many functionally similar parts across subfamilies (standard, LS, HC, etc.). Recognizing part numbers and functions avoids selection errors and simplifies substitutions. Given Data / Assumptions: 7476: dual J–K flip-flop (master–slave or edge-triggered depending on variant), TTL. 74LS76: low-power Schottky (LS) TTL variant of the 7476 with similar pinout/function. “Dual” indicates two flip-flops per package. Concept / Approach: In the 74xx family, base numbers denote function while prefixes/suffixes denote logic subfamily and performance differences. Thus 7476 and 74LS76 share the same logic function: two J–K flip-flops in one IC, but differ in electrical characteristics like speed and power. Step-by-Step Solution: Identify base function 76 = dual J–K flip-flops.Confirm LS indicates low-power Schottky implementation.Hence both 7476 and 74LS76 are dual J–K flip-flops.Therefore, the statement is correct. Verification / Alternative check: Pin-compatible datasheets show near-identical logic diagrams and truth tables; only electrical parameters differ. Why Other Options Are Wrong: Incorrect / “only one is dual” / “monostable”: These contradict established part catalogs and datasheets. Common Pitfalls: Confusing LS/HC/HCT subfamilies with different functions; overlooking that timing and voltage specs change across subfamilies even when logic function is the same. Final Answer: Correct

Flip-Flops Questions