Question 1

In flip-flop terminology, an input that is acted upon only when a qualifying enable or trigger (such as a clock/enable) is present is called a synchronous input. Is the statement “such an input is asynchronous” accurate?

Accepted Answer

Introduction / Context: Digital storage elements, such as latches and flip-flops, are controlled by signals that determine when input data may affect the stored state. Two broad classes of control exist: synchronous (governed by an enable or clock event) and asynchronous (acting immediately, regardless of clock). Understanding this distinction is essential when reading datasheets and designing robust synchronous systems. Given Data / Assumptions: The statement claims that an input accepted only with an enable/trigger present is “asynchronous.” Typical flip-flops include a data input that is sampled on a clock edge (synchronous) and may include direct set/reset inputs (asynchronous). Enable signals for latches and clocks for flip-flops control when data is allowed to pass or be captured. Concept / Approach: Synchronous inputs are qualified by a clock or enable. The device responds only at defined times (level-open window for latches or an edge for flip-flops). Asynchronous inputs bypass this timing control and can change the state at any time, independent of the clock, which is why they are commonly used for reset or preset functions. Step-by-Step Solution: Identify inputs that require a clock or enable (e.g., D on a D flip-flop, gated S/R on a level latch) → synchronous.Identify inputs that act immediately (e.g., direct CLR or PR on a 74xx flip-flop) → asynchronous.Compare to the statement: “only accepted when enable/trigger is present” matches synchronous behavior, not asynchronous.Therefore, the statement is inaccurate. Verification / Alternative check: Datasheets for common devices (e.g., 7474) explicitly list D as clocked (synchronous) and list asynchronous preset/clear separately. Timing diagrams show D is sampled only on edges; asynchronous inputs take effect immediately. Why Other Options Are Wrong: Calling the statement “Correct” reverses the established definitions. Restricting the claim to latches or edge-triggered devices does not fix the core error; synchronous vs asynchronous is independent of level vs edge behavior. Common Pitfalls: Confusing “enable present” with “asynchronous control.” Also, assuming any control not named “clock” is asynchronous—gated latches still operate synchronously with respect to their enable. Final Answer: Incorrect

Question 2

In VHDL for edge-triggered sequential circuits, which construct is the central mechanism used to describe clocked behavior and detect edges (for example, using rising_edge(clk))?

Accepted Answer

Introduction / Context: VHDL supports multiple abstraction levels. For sequential, clocked logic, designers typically use a clocked process to describe how registers update on edges and how state machines transition. Knowing the correct construct for edge-triggered modeling is vital for synthesizable and readable code. Given Data / Assumptions: We need to describe behavior on a clock edge (rising or falling). Standard synthesizable VHDL idioms use if rising_edge(clk) or if falling_edge(clk) within a process. We distinguish between structural/organizational constructs and executable sequential constructs. Concept / Approach: The PROCESS statement encapsulates sequential statements and a sensitivity list (or uses wait statements). For clocked logic, a process is sensitive to the clock and possibly asynchronous reset; inside it, an if rising_edge(clk) block defines register updates. Other constructs (ARCHITECTURE, FUNCTION, VARIABLE) serve different roles: architecture contains processes; functions are combinational subprograms; variables are storage within processes. Step-by-Step Solution: Create a process with a clock (and optional reset) in its sensitivity list.Within the process, use if rising_edge(clk) then … end if to model edge-triggered updates.Assign registered outputs and next-state signals inside the edge clause.Synthesize to infer flip-flops from this description. Verification / Alternative check: Synthesis tools map clocked processes to device registers consistently. Simulation waveforms confirm updates only at edges, matching edge-triggered semantics. Why Other Options Are Wrong: ARCHITECTURE organizes design units but is not itself the executable mechanism. FUNCTIONs are pure/combinational and cannot hold state or directly model edge-triggered storage. VARIABLE refers to an object class, not a structural or behavioral block. Common Pitfalls: Forgetting rising_edge/falling_edge and relying only on the sensitivity list can create level-sensitive behavior. Mixing blocking-like thinking with signal assignment delays can also confuse timing. Final Answer: PROCESS

Question 3

Flip-flop timing: “Setup time” specifies which requirement for reliable data capture relative to the active clock edge?

Accepted Answer

Introduction / Context: Setup time is a fundamental parameter in synchronous design. Violating setup time can lead to metastability or incorrect data capture, undermining reliable system operation. Understanding it helps with clock frequency decisions, placement/route constraints, and timing closure. Given Data / Assumptions: A flip-flop samples its D (or equivalent) input on a particular clock edge. There is a minimum interval before that edge during which the input must be stable. Hold time (after the edge) is a related, but distinct requirement. Concept / Approach: Setup time (t_setup) is the minimum time that the data and relevant control levels must be valid and unchanged before the active clock edge. If data changes too close to the edge, the internal latching circuitry may not settle, risking metastability or capturing the wrong value. Step-by-Step Solution: Identify the active clock edge for the device (rising or falling).Ensure the data path delay plus source clock skew causes the data to be stable at least t_setup before that edge.Verify with static timing analysis that arrival times meet t_setup.If violated, reduce clock frequency, optimize logic, or adjust constraints to increase slack. Verification / Alternative check: Timing simulation and STA reports list setup slack. Positive slack implies requirements are met; negative slack indicates a violation. Why Other Options Are Wrong: Option b confuses setup with a vague “maximum” and output behavior. Option c is irrelevant to timing. Option d defines propagation delay (t_co), not setup. Common Pitfalls: Mixing up setup and hold, or assuming asynchronous resets affect setup—resets have separate constraints. Also, ignoring clock skew/jitter can lead to unexpected violations. Final Answer: the minimum time for the control levels to be maintained on the inputs prior to the triggering edge of the clock in order for data to be reliably clocked into the FF

Question 4

For a 7474 edge-triggered D flip-flop with inputs S, R, D, and CLK, which input(s) are synchronous with respect to the clocked operation?

Accepted Answer

Introduction / Context: The 7474 is a classic dual D flip-flop with asynchronous preset (S) and clear (R). Recognizing which inputs are clock-synchronous is essential when interpreting timing diagrams and preventing unintended state changes in synchronous systems. Given Data / Assumptions: Inputs: D (data), CLK (clock), S (preset), R (clear). S and R on the 7474 are asynchronous (direct set/reset) and can force outputs regardless of the clock. D is sampled on the active (typically rising) clock edge. Concept / Approach: A synchronous input is one whose effect is controlled by the clock event. With the 7474, only D is captured at the active edge; S and R act immediately (subject to their active levels), overriding normal clocked operation. The CLK is not “an input whose effect is synchronous”; it is the timing reference itself. Step-by-Step Solution: Check datasheet truth table: D is transferred to Q only on the specified clock edge.Observe that S (preset) and R (clear) drive Q high/low independent of clock edges.Conclude that only D qualifies as a synchronous input.Therefore, the correct choice is “Only D.” Verification / Alternative check: Timing diagrams show D is latched on clock edges, while asynchronous set/clear dominate immediately when asserted. Why Other Options Are Wrong: “Only S” and “S and R” are incorrect because S and R are asynchronous controls. “All of the above” incorrectly lumps asynchronous controls with the one synchronous data input. Common Pitfalls: Treating preset/clear as if they must wait for a clock; this can cause hazards if asserted unintentionally during normal operation. Final Answer: Only D

Question 5

An edge-triggered flip-flop changes state only under which condition related to its trigger (clock) input?

Accepted Answer

Introduction / Context: Edge-triggered storage elements respond at the instant a clock transitions, not while it remains steady. This property allows precise timing in synchronous systems, enabling designers to coordinate state updates across many registers. Given Data / Assumptions: We are considering an edge-triggered device (not a level-sensitive latch). The “trigger” refers to the clock input of the flip-flop. Edges may be rising or falling depending on the device symbol and configuration. Concept / Approach: Edge-triggering implies that data is sampled and state may change only at the moment the clock transits through its active edge. While the clock remains HIGH or LOW, further changes in D do not propagate to Q until the next active edge. This isolation reduces race and transparency issues common with level-sensitive elements. Step-by-Step Solution: Identify device edge polarity (rising-edge or falling-edge).Ensure D meets setup/hold around that edge.Recognize that Q updates occur at the edge, not while the clock is static.Therefore, the defining condition is the trigger input changes levels (the edge). Verification / Alternative check: Timing diagrams and truth tables for D/JK flip-flops confirm state changes only on edges, provided setup/hold are satisfied and asynchronous controls are inactive. Why Other Options Are Wrong: “Trigger HIGH/LOW” describes level-sensitive behavior, not edge-triggering. “D input HIGH” confuses data value with timing; state changes can occur on edges regardless of whether D is 0 or 1 (subject to the device function). Common Pitfalls: Assuming that any clock activity while HIGH or LOW affects Q (that is true for latches, not edge-triggered flip-flops). Also, forgetting setup/hold can cause metastability, obscuring the apparent edge-triggered operation. Final Answer: the trigger input changes levels

Question 6

The 74121 nonretriggerable one-shot (monostable multivibrator) can be configured so that the output pulse width is set by a single external component. Which component is used in that single-component timing configuration?

Accepted Answer

Introduction / Context: Monostable multivibrators generate a single output pulse of controlled duration in response to a trigger. The 74121 (and similar families) offers flexible timing configurations. Knowing which external parts are required helps when selecting components for pulse-width generation in digital timing circuits. Given Data / Assumptions: Device: 74121 nonretriggerable one-shot. Some configurations use both an external resistor and capacitor (R*C) to set pulse width. The device also provides an internal timing resistor path that allows using a single external capacitor for timing in a particular mode. Concept / Approach: The 74121 supports two timing modes: one using external R and C for a wide range of pulse widths, and another that leverages an internal resistor (selected by pin strapping) so that only an external capacitor determines the time constant. In that single-component mode, the external capacitor charges/discharges through the internal resistor to create the specified pulse width. Step-by-Step Solution: Choose the configuration that enables the internal timing resistor (per datasheet pin connections).Connect only the external timing capacitor to the appropriate pins.Compute approximate pulse width using t_p ≈ k * R_internal * C_ext (k is a device-dependent constant).Trigger the device; observe a fixed-width output pulse defined mainly by C_ext in this mode. Verification / Alternative check: Reviewing application notes for 74121/74LS121 shows the single-capacitor timing option, whereas the 74123 requires both R and C externally for timing. Why Other Options Are Wrong: Inductors are not used in these standard one-shot timing paths. A standalone resistor cannot define timing without a capacitor. An LED is unrelated to timing generation. Common Pitfalls: Confusing the 74121 (with optional internal resistor) and the 74123 (dual retriggerable one-shot requiring external R and C). Also, neglecting capacitor tolerance and temperature coefficients can skew pulse width. Final Answer: capacitor

Question 7

In VHDL structural design, each component instance is written using a label followed by a specific punctuation mark and then the referenced entity/architecture or library primitive name. Which punctuation mark correctly follows the instance label?

Accepted Answer

Introduction / Context: Structural VHDL describes a circuit by instantiating components and wiring ports. The syntax uses labels to identify each instance. Remembering the exact punctuation after the label avoids compilation errors and improves code readability. Given Data / Assumptions: A typical instantiation looks like: my_add: entity work.adder(rtl) port map(...); The label (my_add) identifies this occurrence in the design. After the label comes punctuation before the design unit reference. Concept / Approach: VHDL requires a colon after the instance label to separate it from the unit being instantiated (entity, component, or configuration). After the colon, the designer specifies the entity name, possibly with a library and architecture, followed by the port map association list and ending with a semicolon. Step-by-Step Solution: Write the instance label (e.g., alu0).Insert a colon to indicate the beginning of the instantiation target.Reference the entity/component (e.g., entity work.alu(rtl)).Complete with port map (...) and terminate with a semicolon. Verification / Alternative check: Any VHDL reference or compiler error messages will complain if a semicolon or other token is used in place of the colon after the label. Why Other Options Are Wrong: “function” and “signal” are not punctuation. A semicolon terminates the entire instantiation statement; it does not follow the label. The correct punctuation after the label is the colon. Common Pitfalls: Omitting the colon or misplacing the semicolon causes syntax errors. Also, confusing component instantiation syntax with process or concurrent statement syntax can lead to formatting mistakes. Final Answer: colon

Question 8

In synchronous digital systems, the precise times at which outputs may change state are governed by a system-wide timing reference commonly called the ________.

Accepted Answer

Introduction / Context: Synchronous design coordinates many storage elements and logic paths using a central timing reference, ensuring deterministic updates and simplifying verification. The most important signal in such systems is the clock, which orchestrates when state transitions occur. Given Data / Assumptions: The system uses edge-triggered flip-flops or level-enabled latches synchronized to a global or local clock domain. Outputs change at well-defined edges or windows relative to the clock. Asynchronous inputs are minimized or carefully synchronized. Concept / Approach: The clock defines when flip-flops sample inputs and update outputs. Static timing analysis computes maximum safe clock frequency by ensuring that combinational paths between registers meet setup/hold constraints with respect to the clock edges. Step-by-Step Solution: Distribute the clock with controlled skew and jitter.Use the clock edges to capture data into flip-flops.Ensure data is stable around the edge (setup/hold) for reliable operation.Observe that outputs only change at defined clock events (ignoring asynchronous controls). Verification / Alternative check: Waveforms show that, absent asynchronous actions, registered outputs transition at clock edges only. STA confirms timing closure relative to the clock. Why Other Options Are Wrong: “traffic” is not an engineering term here. “D” is a data pin, not a timing reference. “flip-flop” is an element controlled by the timing reference; it is not the reference itself. Common Pitfalls: Underestimating clock distribution challenges (skew/jitter), or mixing clock domains without proper synchronization can lead to metastability and data corruption. Final Answer: clock

Question 9

For a J–K flip-flop with J = 1 and K = 1 applied before a valid clock edge, what will the next clock pulse cause the output to do?

Accepted Answer

Introduction / Context: The J–K flip-flop generalizes the behavior of S–R and D flip-flops. When both J and K are asserted, the device enters a toggle mode, making it useful as a divide-by-2 counter stage or for state machines that require alternating outputs. Given Data / Assumptions: Inputs J = 1, K = 1 are stable and satisfy setup/hold around the active clock edge. No asynchronous set/reset is active. Current output state Q is either 0 or 1 prior to the clock edge. Concept / Approach: The J–K truth table shows: J = 1, K = 0 → set; J = 0, K = 1 → reset; J = K = 0 → no change; J = K = 1 → toggle. Thus, each active edge in this condition complements the present state, creating a square wave at half the clock frequency at Q. Step-by-Step Solution: Assume Q(n) is the pre-clock value.Apply J = 1, K = 1 with proper timing.On the next clock edge, the device computes Q(n+1) = ~Q(n).Therefore, the output toggles each qualified clock, dividing frequency by 2. Verification / Alternative check: Simulate successive clock edges with J = K = 1; observe Q sequence 0→1→0→1… if starting at 0 (or the inverse if starting at 1). Why Other Options Are Wrong: “set” and “reset” correspond to J = 1, K = 0 or J = 0, K = 1, not J = K = 1. “latch” implies level-sensitive behavior, not edge-triggered toggling on a J–K flip-flop. Common Pitfalls: Forgetting setup/hold can break toggle behavior. Also, wiring feedback to create a T flip-flop must ensure glitch-free J and K inputs. Final Answer: toggle

Question 10

If an input action is initiated by a signal transition (a change from 0→1 or 1→0) rather than by a sustained level, that input is said to be ________.

Accepted Answer

Introduction / Context: In digital electronics, how a device responds to a control signal—on an edge or on a level—shapes timing behavior and design methodology. Edge-triggering provides precise timing points, whereas level-sensitive control allows action over a window while the level is asserted. Given Data / Assumptions: The device action occurs upon a transition of the control input (rising or falling edge). While the input remains high or low, no additional action occurs until the next edge. Terms used should reflect standard engineering vocabulary. Concept / Approach: “Edge-triggered” describes activation tied to a change in the control signal. Typical examples are flip-flops that sample data on rising_edge(clk) or falling_edge(clk). In contrast, “level-sensitive” latches respond as long as the enable remains active. Pulse-triggered may describe one-shots that respond to a narrow pulse, but the defining concept here is the edge itself. Step-by-Step Solution: Identify the nature of activation: transition-based or level-based.For transition-based activation, label it “edge-triggered.”Associate common devices (D/JK flip-flops) with edge-triggered behavior.Reserve other terms for different mechanisms (monostable pulses, line-level gating). Verification / Alternative check: Timing diagrams of standard flip-flops show state changes only at clock edges. No changes occur while the clock level is steady, confirming edge sensitivity. Why Other Options Are Wrong: “hair-triggered” is not a formal term. “line-triggered” is ambiguous and nonstandard. “pulse-triggered” emphasizes a pulse occurrence rather than the edge itself; many edge-triggered circuits do not require a narrow pulse, just a qualifying edge. Common Pitfalls: Confusing edge-triggered flip-flops with level-sensitive latches, leading to unintended transparency and race conditions if misapplied. Final Answer: edge-triggered

Question 11

HDL versus schematic-based design entry in digital electronics Complete the statement with the most appropriate choice: “Most people would prefer to use ________ over a Hardware Description Language (HDL) when describing or communicating small to me…

Accepted Answer

Introduction / Context: When engineers capture digital logic, they can choose between text-based Hardware Description Languages (HDLs) such as VHDL/Verilog/AHDL and visual schematic or block-diagram representations. This question probes practical preferences for communication and early-stage design work rather than final implementation method. Given Data / Assumptions: “Most people” refers to students, technicians, and engineers collaborating across mixed-experience teams. Target context includes introducing logic functions, explaining data flow, and documenting small to medium designs. HDLs remain essential for synthesis, simulation, and large designs, but are not always the most intuitive starting point. Concept / Approach: Graphic descriptions (schematics, block diagrams, timing diagrams) present signals and connectivity spatially. Humans quickly infer relationships such as enable gating, multiplexing, and feedback. HDLs are compact and powerful, but the learning curve and abstraction can make quick, broad communication harder for non-specialists. Step-by-Step Solution: Identify the goal: fast comprehension across a mixed audience.Compare modalities: HDL (textual, precise) versus graphics (visual, intuitive).For communication and early prototyping, choose the medium that reduces cognitive load: graphic descriptions.Therefore, the blank is best filled by “graphic descriptions.” Verification / Alternative check: In design reviews and classroom settings, schematics and block diagrams are routinely used to explain ideas even when the implementation will ultimately be written in HDL and synthesized. Why Other Options Are Wrong: “Functions” is vague and not a complete design-entry modality. “VHDL” and “AHDL” are HDLs; the stem asks for a preference over HDL, not another HDL. Common Pitfalls: Assuming HDL is always superior; overlooking audience background; neglecting that large-scale designs still require HDL despite early graphic sketches. Final Answer: graphic descriptions

Question 12

Schmitt trigger input advantage in flip-flop and logic interfacing What is the major advantage of using a Schmitt trigger input stage on a digital device?

Accepted Answer

Introduction / Context: Schmitt trigger inputs add hysteresis to a digital device's input threshold, meaning the rising and falling switching points are separated. This is extremely useful when dealing with slow, noisy, or analog-like input waveforms that would otherwise cause multiple unwanted transitions. Given Data / Assumptions: Input signals may contain noise, ringing, or slow slew rates. We are comparing devices with standard CMOS/TTL thresholds versus Schmitt-trigger thresholds. Goal: obtain a single, clean transition at the output when the input crosses the threshold region. Concept / Approach: Hysteresis implements two distinct thresholds: Vth+ for rising signals and Vth− for falling signals. Once the input crosses Vth+, the output switches and remains latched until the input falls below Vth−. This eliminates chatter around the switching region and provides excellent noise immunity. Step-by-Step Solution: Consider a noisy ramp entering a conventional input: the output may toggle repeatedly as noise traverses a single narrow threshold.Replace with a Schmitt input: rising must exceed Vth+ to switch once; falling must drop below Vth− to switch back.The separation Vth+ − Vth− filters small oscillations in the threshold region.Therefore, the primary benefit is avoidance of erratic triggering. Verification / Alternative check: Oscilloscope comparisons with and without Schmitt hysteresis show the jitter-free switching waveform at the device output when hysteresis is present. Why Other Options Are Wrong: “More triggering methods” and “wider range of outputs” are unrelated to input hysteresis. “Can be retriggered” describes monostables, not Schmitt inputs. Common Pitfalls: Confusing Schmitt inputs with debounce circuits; assuming hysteresis fixes gross noise without proper filtering; ignoring that threshold values vary by logic family. Final Answer: avoids erratic triggering

Question 13

Verifying HDL designs — tool used regardless of AHDL or VHDL source Regardless of whether you describe the circuit in AHDL or VHDL, the correct way to verify proper operation is to use a ________.

Accepted Answer

Introduction / Context: HDLs enable text-based descriptions of logic. Verification ensures the design behaves as intended before hardware implementation. This question focuses on the standard verification workflow after coding in AHDL or VHDL. Given Data / Assumptions: The design is already written in a supported HDL. We need a method to validate functionality across test vectors and timing scenarios. Target flow includes analysis, elaboration, and dynamic checking of waveforms. Concept / Approach: A simulator evaluates HDL processes and concurrent statements to produce time-ordered waveforms. Designers apply stimulus (testbenches), observe responses, and compare them with specifications. This is independent of the source HDL dialect; VHDL and AHDL alike need simulation to catch functional and timing issues early. Step-by-Step Solution: Write or import the HDL description and associated testbench.Run behavioral simulation to verify logic-level functionality.Optionally run post-synthesis or gate-level simulation to include propagation delays and constraints.Iterate until outputs match expected results for all relevant vectors. Verification / Alternative check: Static timing analysis complements simulation but does not replace functional verification. Hardware prototyping (e.g., on FPGA) is later-stage validation, not the primary verification step following HDL coding. Why Other Options Are Wrong: “PROCESS” is a VHDL keyword, not a verification tool. “Computer” is too generic. “Primitive library” provides building blocks, not verification. Common Pitfalls: Relying solely on synthesis without simulation; inadequate testbench coverage; ignoring corner cases and reset behavior. Final Answer: simulator

Question 14

NOR-gate S–R latch: deducing inputs from the outputs Given a cross-coupled NOR-gate S–R flip-flop has outputs Q = 0 and Q̄ = 1 (the stable reset state), determine the required S and R input levels.

Accepted Answer

Introduction / Context: The cross-coupled NOR S–R latch is a fundamental memory element. Knowing one of its stable output states lets us infer which inputs could have produced or are maintaining that state. Here the outputs are Q = 0 and Q̄ = 1, which is the conventional reset state. Given Data / Assumptions: Latch type: S–R using NOR gates, active-high inputs. Outputs observed: Q = 0 and Q̄ = 1. We seek steady-state inputs consistent with the observed outputs (not the transient drive used to reach it). Concept / Approach: For a NOR-based latch: a logic 1 on S forces Q = 1; a logic 1 on R forces Q = 0. When both S and R are 0, the latch holds the prior state. The illegal condition is S = R = 1 because both outputs would be 0, violating complementarity. Step-by-Step Solution: Given Q = 0 and Q̄ = 1, the state is RESET.A sufficient input combination to force this is R = 1 and S = 0 (R dominates Q to 0 via NOR gating).After the state is reached, R can be returned to 0 to hold; however, the question focuses on inputs that correspond to (or maintain) Q = 0 and Q̄ = 1.Thus, S = 0, R = 1 is the direct forcing combination. Verification / Alternative check: Truth behavior: NOR with R = 1 ensures its output (feeding Q) is 0 regardless of feedback; the complementary side remains 1, confirming Q̄ = 1. Why Other Options Are Wrong: “S = 1, R = 1” is invalid. “S = 1, R = 0” would set Q = 1. “S = 0, R = 0” simply holds the previous state but does not necessarily explain how Q became 0 if it were previously 1. Common Pitfalls: Confusing NOR and NAND latch polarities; overlooking that S = R = 0 is a hold, not a force, condition. Final Answer: S = 0, R = 1

Question 15

Flip-flop asynchronous controls — standard labels and polarity The asynchronous inputs on common flip-flops are normally labeled ________ and ________, and they are normally active-________ inputs.

Accepted Answer

Introduction / Context: Many flip-flops include asynchronous controls that can immediately force the stored state independent of the clock. Recognizing their standard labels and active polarity is crucial for reset strategy and power-up behavior in digital systems. Given Data / Assumptions: Common families (TTL/CMOS) provide direct PRESET (set) and CLEAR (reset) pins. Datasheets frequently denote these inputs with overbars or bubbles indicating active-low behavior. Asynchronous controls override synchronous data inputs when asserted. Concept / Approach: “PRE” (preset) forces Q = 1, “CLR” (clear) forces Q = 0. The normal convention is active-low: PRĒ and CLR̄. Bubbles on the symbol pins or the bar notation communicate that a logic 0 asserts the function. Step-by-Step Solution: Identify the usual labels: PRE and CLR.Recognize active-low polarity from symbols or pin names.Conclude: PRE, CLR, LOW is the correct completion. Verification / Alternative check: Check any standard 74xx or 4000-series flip-flop datasheet (e.g., 74HC74 D-FF): asynchronous clear is active low; parts with preset also use active-low notation. Why Other Options Are Wrong: “ON/OFF/HIGH” and “START/STOP/LOW” are not standard labels. “SET/RESET/HIGH” describes synchronous naming and the wrong polarity for typical asynchronous control pins. Common Pitfalls: Failing to synchronize the deassertion of asynchronous resets; ignoring minimum pulse width; assuming polarity without checking the symbol. Final Answer: PRE, CLR, LOW

Question 16

Classifying a latch among multivibrators What type of multivibrator is a latch, considering its number of stable states and behavior?

Accepted Answer

Introduction / Context: Multivibrators are grouped by stability: astable (no stable state), monostable (one stable state), and bistable (two stable states). Latches and flip-flops store one bit by holding one of two stable outputs until inputs command a change. Given Data / Assumptions: A latch can remain indefinitely in either of two states without a clock. Inputs such as S/R or D with enable determine which state is captured. No internal oscillation occurs in steady conditions. Concept / Approach: A device is bistable if it has two stable equilibrium points and transitions between them on command. An SR latch made from cross-coupled gates, or a gated D latch, satisfies this definition perfectly: it “remembers” a 0 or 1 until directed otherwise. Hence, a latch is a bistable multivibrator. Step-by-Step Solution: Consider SR latch: it can be SET or RESET and stay there.Enable-controlled (level) latches pass input while enabled, then hold when disabled.Both behaviors indicate two stable states and memory retention.Therefore, the correct classification is bistable. Verification / Alternative check: Block diagrams and textbooks consistently identify latches and flip-flops as bistable elements. Why Other Options Are Wrong: Astable oscillates continuously (no stable state). Monostable requires a trigger to leave and then return to its single stable state. “Depends on type” is misleading; regardless of SR or D style, latches are bistable. Common Pitfalls: Confusing latches with one-shots or oscillators; overlooking that transparency during enable does not negate bistability when disabled. Final Answer: Bistable

Question 17

Retriggerable one-shot timing — extending pulse width with a second trigger A retriggerable monostable has nominal pulse width 10 ms. It is triggered, and 3 ms later another trigger arrives. What is the resulting total output pulse width (in ms)?

Accepted Answer

Introduction / Context: Retriggerable one-shots (retriggerable monostables) produce an output pulse of fixed nominal width T after each valid trigger. If a new trigger arrives while the output is still active, the timing interval restarts, effectively extending the pulse. Understanding this behavior is important for pulse stretching and missing-pulse detection. Given Data / Assumptions: Nominal width T = 10 ms per trigger. First trigger at t = 0 ms; second trigger at t = 3 ms. Device is retriggerable (new triggers restart the timing window). Concept / Approach: For a retriggerable device, the output stays high for T after the most recent trigger. Each time a new trigger arrives during the active pulse, the expiration time becomes (time of latest trigger + T). Step-by-Step Solution: Initial trigger at 0 ms starts a 10 ms pulse, scheduled to end at 10 ms.Second trigger at 3 ms restarts timing; new planned end time = 3 ms + 10 ms = 13 ms.No further triggers occur; therefore, the total high time since t = 0 ms is 13 ms.Hence, the resulting pulse width is 13 ms. Verification / Alternative check: Draw a time line: high from 0–13 ms with a restart at 3 ms; waveform matches vendor timing diagrams for retriggerable monostables (e.g., 74HC123). Why Other Options Are Wrong: 3 and 7 ms confuse remaining time vs. total. 10 ms ignores the retrigger. Only 13 ms reflects the restart behavior. Common Pitfalls: Mixing retriggerable with non-retriggerable behavior; forgetting that the second trigger must meet minimum pulse width and re-arm conditions. Final Answer: 13

Question 18

Gated S–R flip-flop (enable-controlled) — condition for CLEAR output A gated S–R flip-flop goes to the CLEAR state under which input condition?

Accepted Answer

Introduction / Context: Gated S–R flip-flops include an enable (EN) input that qualifies when the S and R inputs may affect the internal latch. Understanding how EN gates the set/reset commands is essential for designing control logic. Given Data / Assumptions: Active-high enable: S and R are effective only when EN = 1. Active-high S sets Q = 1; active-high R resets (clears) Q = 0. When EN = 0, the device ignores S and R and holds its state. Concept / Approach: To force CLEAR (Q = 0), the reset input must be asserted while the gate allows it to pass to the latch. Thus R must be high and EN must be high at the same time. S must be low to avoid the invalid or conflicting input combination. Step-by-Step Solution: Ensure EN = 1 so inputs can act on the latch.Apply R = 1 and S = 0 to command a reset (clear).Latch drives Q → 0 and Q̄ → 1, entering CLEAR.Maintain or release inputs as required; with EN low, state is held. Verification / Alternative check: Examine the truth table of a gated S–R latch: with EN = 1, S = 0, R = 1 leads to Q(next) = 0. With EN = 0, inputs have no effect. Why Other Options Are Wrong: Option A sets, not clears. Option C has EN low, so no action occurs. Option D also has EN low, preventing state change. Common Pitfalls: Forgetting EN polarity; asserting both S and R simultaneously; confusing NAND- and NOR-based latch polarities. Final Answer: S is LOW; R is HIGH; EN is HIGH

Question 19

Symbol recognition — identifying edge-triggered flip-flops on schematics Which symbol feature is used to identify an edge-triggered flip-flop on its clock input?

Accepted Answer

Introduction / Context: Schematic symbols encode behavior. Flip-flops can be level-sensitive or edge-triggered, and recognizing the visual cues on the clock pin helps engineers quickly understand timing without consulting a full datasheet. Given Data / Assumptions: Triangle on the clock input denotes edge-triggering. An added bubble indicates inversion (falling-edge sensitivity). No triangle usually implies a level-sensitive latch (enable-controlled transparency). Concept / Approach: The triangle shape is the canonical indicator of edge sensitivity. If a bubble accompanies it, the device triggers on the negative-going edge; without the bubble, it triggers on the positive-going edge. This convention is consistent across major schematic standards. Step-by-Step Solution: Inspect the clock pin symbol.If a triangle is present, classify the element as edge-triggered.Check for a bubble to determine edge polarity.Thus the correct identification feature is the triangle. Verification / Alternative check: Compare with logic textbooks and vendor symbol guides; all employ the triangle for edge-triggered flip-flops. Why Other Options Are Wrong: A bubble alone indicates inversion, not necessarily edge behavior. An inverted “L” is not a standard indicator. The letter “E” typically labels an enable pin, unrelated to edge-triggering. Common Pitfalls: Confusing enable pins with clock pins; misinterpreting bubble polarity; assuming edge type without checking the bubble. Final Answer: a triangle on the clock input

Question 20

Gated D latch fundamentals — identify the missing feature: A “gated D latch” is a level-sensitive storage element that uses a D (data) input and an enable (also called G or EN) control to become transparent when enabled and to hold its state when di…

Accepted Answer

Introduction / Context: Latches and flip-flops are the foundational storage elements in digital electronics. A “gated D latch” is a level-sensitive device whose transparency is controlled by an enable signal rather than by an edge-triggered clock. Distinguishing what a gated D latch does and does not have helps learners avoid confusing it with edge-triggered D flip-flops. Given Data / Assumptions: The device in question is a standard gated D latch (sometimes denoted as D latch with EN or G). The latch has a D input, Q output (and often Q’), and an enable control that governs transparency. We are comparing the presence or absence of a dedicated clock input versus an enable input. Concept / Approach: A gated D latch is level-sensitive: when EN is active (for example, EN = 1 for a positive-level latch), the output Q follows D; when EN is inactive, Q holds the last state. Edge-triggered devices (flip-flops) use a clock and respond at transitions. Thus, a gated D latch does not require a dedicated clock input; its control is the enable/gate signal. Step-by-Step Solution: Identify device nature: level-sensitive (not edge-triggered).List typical pins: D, Q (and Q’), EN (or G). Optional asynchronous clear/preset may exist but are not required.Compare with flip-flop: flip-flops require a clock input; latches do not.Conclude: the missing feature on a basic gated D latch is a dedicated clock input. Verification / Alternative check: Examine timing diagrams: Q tracks D only during the enable’s active level, not at a clock edge—another indicator there is no clock pin. Why Other Options Are Wrong: an enable (gate) input: This defines when the latch is transparent; it is essential for a gated latch.a Q output terminal: Every latch must expose its stored state; Q is fundamental.internal steering/gating logic: Implementations commonly use transmission gates or gating networks to realize level control; these certainly exist. Common Pitfalls: Confusing latches (level-sensitive) with flip-flops (edge-triggered).Assuming “enable” and “clock” are interchangeable; they are not. Final Answer: a dedicated clock input

Flip-Flops Questions