Question 1

Positive edge-triggered flip-flop behavior — when are inputs sampled? A positive edge-triggered flip-flop changes state only at the active (rising) clock transition. Complete the statement: “A positive edge-triggered flip-flop will accept (sample) i…

Accepted Answer

Introduction / Context: Synchronous sequential circuits rely on edge-triggered flip-flops to register data at precise instants. Understanding exactly when a positive edge-triggered flip-flop samples its inputs is crucial for proper timing closure, meeting setup/hold times, and avoiding metastability in digital systems. Given Data / Assumptions: The device is a positive edge-triggered flip-flop (for instance, a D or J-K with a positive edge clock). Setup time (tsu) and hold time (th) constraints must be satisfied around the sampling edge. Asynchronous controls, if any, are inactive and do not influence the normal sampling behavior. Concept / Approach: By definition, a positive edge-triggered flip-flop samples its inputs at the instant the clock transitions from LOW to HIGH. Data present at the input must be stable for a window that starts tsu before the edge and continues through th after the edge. The output Q updates as a result of this sampling and remains stable until the next active edge (ignoring asynchronous overrides). Step-by-Step Solution: Recognize the sampling instant: the rising edge of the clock.Relate to timing: inputs must be valid during [edge − tsu, edge + th].Eliminate distractors: clock level (HIGH or LOW) does not define sampling for edge-triggered devices.Select correct completion: “changes from LOW to HIGH.” Verification / Alternative check: Timing diagrams show Q updating at the clock’s rising edge, not throughout the HIGH level. Why Other Options Are Wrong: is LOW / is HIGH: These describe levels (latch-like behavior), not edges.changes from HIGH to LOW: That is the negative edge condition, not positive. Common Pitfalls: Confusing level-sensitive latches with edge-triggered flip-flops.Ignoring setup/hold margins near the active edge. Final Answer: changes from LOW to HIGH

Question 2

Gated S-R latch (gated S-R “flip-flop”) hold behavior: Under which condition does a gated S-R storage element remain in the hold (no-change) state while it is enabled?

Accepted Answer

Introduction / Context: A gated S-R latch adds an enable (gate) control to the basic S-R latch so that input commands are effective only when the gate is asserted. Knowing the exact condition that causes a hold (no change) while enabled helps avoid accidental state changes and race-through issues in combinational-to-sequential interfaces. Given Data / Assumptions: Device: gated S-R latch with inputs S, R, and a Gate Enable (often E or G). Active gate level is assumed HIGH (common textbook convention). We are asking for the condition that yields “no change” while enabled. Concept / Approach: The gated S-R truth table typically includes: E=1, S=0, R=0 → no change; E=1, S=1, R=0 → set; E=1, S=0, R=1 → reset; E=1, S=1, R=1 → invalid; and for E=0 the latch ignores S and R and simply holds. The question explicitly focuses on the hold condition when the device is enabled, so we select E=1 with S=0 and R=0. Step-by-Step Solution: Confirm active enable level: Gate Enable HIGH means inputs are “looked at.”Identify hold row in the truth table: S=0 and R=0 gives “no change.”Combine: E=1 and S=R=0 implies enabled but holding.Hence, the correct condition is “Gate Enable HIGH and S and R both LOW.” Verification / Alternative check: Cross-check with a standard truth table from textbooks or datasheets; the mapping is consistent. Why Other Options Are Wrong: the Gate Enable is HIGH: Incomplete—S and R values must be specified.the Gate Enable is LOW: This also produces hold, but the question asks for the enabled case.the S and R inputs are both LOW: Incomplete without the enable context. Common Pitfalls: Forgetting that “enabled” narrows the condition subset.Confusing the enabled hold with the disabled ignore case. Final Answer: the Gate Enable is HIGH and the S and R inputs are both LOW

Question 3

Symbol interpretation — postponed output marking on flip-flop symbols: Some schematic symbol conventions show a special “postponed” mark at the output of a flip-flop. This annotation indicates that the output change is associated with a specific clo…

Accepted Answer

Introduction / Context: Logic-symbol annotations convey timing semantics without long notes. Bubbles, triangles, and auxiliary marks denote active polarities and edge sensitivities. A “postponed” marking at a flip-flop’s output is one such convention that indicates the output’s relationship to clock edges. Given Data / Assumptions: We refer to symbol conventions where outputs may be annotated to show when state changes appear. Edge sense (leading vs. trailing) is the key attribute being identified. Device family specifics may vary, but the core meaning is consistent: postponed output corresponds to a defined edge relation. Concept / Approach: Standard symbolism uses a triangle at the clock input to show edge triggering and a bubble to indicate inversion (e.g., negative-edge). Some libraries further annotate outputs to clarify that the visible change at Q is “postponed” to a particular edge (often the trailing edge in a master-slave implementation). This communicates that although internal storage may occur earlier, the observable output transition appears on the specified edge. Step-by-Step Solution: Recognize what the postponed mark conveys: an intentional delay/link to a particular clock edge.Differentiate from pulse-triggered: monostables/timers use pulses rather than stable edges for state capture.Conclude that the symbol identifies the output as trailing edge-triggered. Verification / Alternative check: Check design guides where master-slave behavior is illustrated: internal latching occurs first, but output “postpones” until the next (trailing) edge. Why Other Options Are Wrong: a D flip-flop / a J-K flip-flop: Type identification is not the purpose of the postponed mark.pulse triggered: Pulse-triggering is a different concept related to one-shots or dynamic transmission-gate structures, not specifically the postponed output marking. Common Pitfalls: Assuming every symbol set uses identical annotations; always check the legend for the drafting standard in use.Confusing input edge symbols (at the clock pin) with output annotations. Final Answer: trailing edge-triggered

Question 4

NOR-based S-R latch operation — identifying the hold (no-change) input combination: For the classic cross-coupled NOR gate S-R latch, which S and R input combination produces the HOLD (no state change) condition?

Accepted Answer

Introduction / Context: The simplest memory element in digital logic is the S-R latch constructed from two cross-coupled NOR gates. Knowing which input combinations set, reset, or hold the state is essential for analyzing asynchronous hazards and for building higher-level sequential elements. Given Data / Assumptions: Latch type: two NOR gates cross-coupled, inputs labeled S (set) and R (reset). Inputs are active-HIGH (typical for NOR-based latches). Outputs are Q and Q’ with mutual feedback. Concept / Approach: For a NOR-latch, active-HIGH S forces Q = 1 (set), and active-HIGH R forces Q = 0 (reset). When both S and R are LOW, neither gate’s direct input asserts, so feedback maintains the existing state. If both S and R are HIGH simultaneously, both outputs are driven LOW, producing an invalid/forbidden condition because Q and Q’ are no longer complements after inputs return LOW. Step-by-Step Solution: S=1, R=0 → Q is driven HIGH (set).S=0, R=1 → Q is driven LOW (reset).S=0, R=0 → no direct drive; outputs stay latched (HOLD).S=1, R=1 → invalid state (both outputs LOW for NOR implementation). Verification / Alternative check: Trace gate equations: Q = NOR(R, Q’), Q’ = NOR(S, Q). With S=R=0, each gate output depends only on the feedback term, preserving state. Why Other Options Are Wrong: S=1, R=1: forbidden/invalid for NOR latch.S=1, R=0 and S=0, R=1: these force set or reset, not hold. Common Pitfalls: Mixing NOR and NAND latch conventions (active-LOW vs. active-HIGH control).Forgetting that S=R=1 is forbidden for NOR latches. Final Answer: S = 0, R = 0

Question 5

Why J-K flip-flops are favored over basic S-R latches in synchronous designs: Identify the key advantage of the J-K flip-flop relative to the S-R flip-flop/latch.

Accepted Answer

Introduction / Context: The S-R storage primitive is simple but suffers from a forbidden input combination that complicates reliable operation. The J-K flip-flop generalizes S-R behavior to remove this invalid case, making it highly useful in synchronous counters and finite-state machines. Given Data / Assumptions: S-R latch/flip-flop has a forbidden state (S=R=1 for NOR, or S̅=R̅=0 for NAND versions). J-K flip-flop introduces inputs J and K that map to set, reset, hold, and toggle behaviors under clock control. We compare device properties for robust synchronous design. Concept / Approach: The hallmark of the J-K is that the “both inputs asserted” case is defined as toggle, not forbidden. Thus, there is no invalid input combination in normal synchronous operation, provided setup/hold are met. This clears a major usability hurdle present with S-R devices. Step-by-Step Solution: Map S-R caveat: S=R=1 produces an illegal state (for NOR implementation).Map J-K behavior: J=1, K=1 → toggle at the active clock edge (Q(next)=Q’).Implication: J-K safely supports all input combinations, hence “no invalid states.” Verification / Alternative check: Examine truth tables: S-R has a forbidden row; J-K has a defined action for every row. Why Other Options Are Wrong: it has fewer gates: Often more complex than S-R; not the advantage.it has only one output: J-K devices present Q and Q’ like others.it does not require a clock input: J-K flip-flops are typically clocked. Common Pitfalls: Assuming “toggle” means asynchronous behavior; toggling is clocked.Confusing latches with edge-triggered flip-flops. Final Answer: it has no invalid states

Question 6

Identifying the major drawback of a basic S-R latch: Among the listed characteristics, which one is the well-known limitation that makes the raw S-R latch less convenient than more advanced primitives such as J-K or D devices?

Accepted Answer

Introduction / Context: The S-R latch is widely taught because it illustrates fundamental bistable feedback. However, one of its input combinations leads to an undefined or forbidden state, and this drawback motivates the use of J-K and D-type primitives in many designs. Given Data / Assumptions: We consider the classic S-R latch using NOR (active-HIGH) or NAND (active-LOW) gating. Outputs are Q and Q’ with complementary feedback. We assess which listed characteristic is the key limitation in practical use. Concept / Approach: For a NOR-based S-R latch, S=1 and R=1 is invalid since both outputs are forced LOW before returning to indeterminate complements. For a NAND-based latch, S̅=0 and R̅=0 is the forbidden case. This invalid/undefined condition complicates input conditioning and can cause racing or metastability if not carefully avoided. Step-by-Step Solution: List behaviors: set, reset, hold, and forbidden.Identify the problematic combination depending on gate type.Conclude that the “invalid condition” is the main drawback. Verification / Alternative check: Compare with J-K: the same corner is defined as toggle, eliminating the invalid state. Why Other Options Are Wrong: complexity: S-R is actually simpler than J-K or D.slow speed: Speed depends on technology; not the defining drawback.latch mode: Being a latch is not inherently a drawback; it is a feature (level sensitivity). Common Pitfalls: Mixing NOR and NAND conventions and forgetting which combination is forbidden.Assuming invalid state is harmless; it can produce unpredictable results. Final Answer: invalid condition

Question 7

Terminology in sequential logic — what does “resetting” a flip-flop or latch mean? Choose the common action term that is synonymous with putting the device into its reset state.

Accepted Answer

Introduction / Context: Consistent terminology prevents confusion when reading datasheets and communicating design intent. In sequential logic, multiple words may describe the same control action, and knowing the standard synonyms speeds collaboration and troubleshooting. Given Data / Assumptions: A flip-flop or latch can be forced to a known state by control inputs labeled RESET, CLEAR, PRESET, or SET (names vary by vendor). “Resetting” typically means driving Q to 0 (while presetting means driving Q to 1). We seek the conventional word that matches “resetting.” Concept / Approach: Industry usage treats “reset” and “clear” as near-synonyms when Q is forced LOW. Devices may label the control pin as CLR, RST, or RESET̅ (active-LOW). Therefore, “clearing” is the standard action term corresponding to resetting the device to zero. Step-by-Step Solution: Define reset: force Q=0, typically via asynchronous input.Match common synonyms: “clear” ≈ “reset” (to zero).Select “clearing” as the term synonymous with resetting. Verification / Alternative check: Survey datasheets: pins labeled CLR, /CLR, RST, or /RST perform the reset/clear function. Why Other Options Are Wrong: breaking / freeing / changing: These do not carry standard, precise meanings in this context. Common Pitfalls: Confusing “preset” (set to 1) with “reset/clear” (set to 0).Assuming reset is always asynchronous; some designs implement synchronous clear. Final Answer: clearing

Question 8

Timing definitions — identify the interval immediately following the active clock transition: In flip-flop timing, the “setup” interval occurs before the sampling edge. What is the name of the critical interval immediately after that active clock tr…

Accepted Answer

Introduction / Context: Correctly applying setup and hold time constraints is essential to reliable synchronous design. Violations cause metastability, unpredictable outputs, or intermittent bugs that are hard to reproduce. Designers must clearly distinguish which time window applies before and which applies after the active clock edge. Given Data / Assumptions: We speak about edge-triggered flip-flops sampling data at the active edge. Setup time (tsu): minimum time that input must be stable before the edge. Hold time (th): minimum time that input must remain stable after the edge. Concept / Approach: The data presented to a flip-flop must meet both constraints to ensure correct latching. While “setup time” protects the sampling action leading into the edge, “hold time” ensures that the sampling latch does not see the input change too soon after the edge when internal transients are still resolving. Step-by-Step Solution: Identify the event: the active clock transition (e.g., rising edge).Ask which interval follows the event: the answer is “hold time.”Confirm definitions: setup precedes, hold follows.Therefore, the correct name is “hold time.” Verification / Alternative check: Examine timing diagrams: note the tsu window before the edge and the th window after the edge. Why Other Options Are Wrong: setup time: This precedes the edge.over-time / hang-time: Nonstandard, informal terms; not used in timing specifications. Common Pitfalls: Treating setup as more important than hold; both are mandatory.Ignoring clock skew and data path delays that can create hold violations even when setup is met. Final Answer: hold time

Question 9

Toggle mode definition — which device changes state on every qualifying clock pulse? Select the option that correctly completes the statement: “In toggle mode, a ________ changes state with each clock pulse.”

Accepted Answer

Introduction / Context: Many counters and frequency dividers rely on a storage element that inverts its state every clock. Recognizing which device exhibits this behavior underlies the design of divide-by-two stages, ripple counters, and synchronous counters. Given Data / Assumptions: The term “toggle mode” refers to an operating condition where Q(next) = Q’(current). A J-K flip-flop with J=K=1, or a T flip-flop with T=1, toggles at each active edge. Edge-detectors and “toggle detectors” are not storage elements; they do not inherently hold and alternate the state. Concept / Approach: A flip-flop is a bistable element. When configured to toggle (J=K=1 for J-K, T=1 for T-type), it changes its state on every active clock edge, producing a square wave at half the input clock frequency. Neither a mere logic “level” nor a detector circuit fulfills the storage and inversion requirements of toggle mode. Step-by-Step Solution: Identify devices capable of storing state: flip-flops (D, J-K, T).Recognize toggle configurations: J=K=1 or T=1.Conclude: the device that changes state each qualifying clock pulse is a flip-flop in toggle mode. Verification / Alternative check: Example: A J-K flip-flop with J=K=1 divides the input clock frequency by 2 at Q. Why Other Options Are Wrong: logic level: Not a device; cannot toggle on its own.edge-detector circuit: Produces narrow pulses, not bistable toggling.toggle detector: Not a standard bistable; typically a sensing circuit. Common Pitfalls: Assuming any periodic signal implies a toggling storage element; toggling specifically refers to a bistable’s state inversion. Final Answer: flip-flop

Question 10

NAND-based S–R latch behavior at forbidden inputs: Assume an S–R latch constructed from cross-coupled NAND gates (active-LOW inputs labeled S̄ and R̄). If both inputs are forced to 0 at the same time, what will the two outputs (Q and Q̄) be?

Accepted Answer

Introduction / Context: This question examines the forbidden-input behavior of a basic S–R latch implemented with cross-coupled NAND gates. Understanding how the outputs respond when both active-LOW control inputs (S̄ and R̄) are driven LOW is crucial for reliable digital design. It reinforces the difference between valid control combinations and the one invalid combination that designers must avoid when using NAND-based S–R latches. Given Data / Assumptions: Latch topology: cross-coupled NAND gates forming an S̄–R̄ latch. Inputs are active-LOW (a 0 is an asserted Set or Reset). Both inputs are simultaneously 0. No propagation delays or analog effects are modeled beyond the ideal logic behavior. Concept / Approach: In a NAND-based S̄–R̄ latch, the valid operating region excludes the case where S̄ = 0 and R̄ = 0 simultaneously. When either input is asserted LOW by itself, the latch sets or resets accordingly. However, asserting both LOW forces both NAND outputs HIGH, which violates the requirement that Q and Q̄ be logical complements. This is the classic “forbidden” or invalid input combination for the NAND S–R latch. Step-by-Step Solution: Recognize that for a NAND gate, any input at 0 forces the output to 1.With S̄ = 0, the top NAND output is forced to 1 regardless of feedback.With R̄ = 0 at the same time, the bottom NAND output is also forced to 1.Therefore, Q = 1 and Q̄ = 1, which is contradictory to the usual complementary relationship. Verification / Alternative check: Draw the two NAND gates and apply the input levels. Each gate sees a 0 on one input, so both outputs must be 1. This direct gate-level reasoning verifies the result without needing timing diagrams. Why Other Options Are Wrong: Q = 0 and Q̄ = 0: For NAND gates, a 0 on any input yields a 1 at the output, so this cannot occur here. Q = 1 and Q̄ = 0 or Q = 0 and Q̄ = 1: These are valid complementary states, but they do not result from the 0,0 input condition on a NAND S–R latch. Outputs oscillate at the clock frequency: The basic latch has no clock; oscillation is not expected from static inputs. Common Pitfalls: Confusing NAND- and NOR-based S–R latches; forgetting that the invalid combination differs between active-HIGH (NOR) and active-LOW (NAND) implementations; assuming a clock is present in a latch; expecting complementary outputs even under forbidden inputs. Final Answer: Q = 1 and Q̄ = 1

Question 11

State terminology in sequential logic: In flip-flop and latch timing descriptions, the term “hold” always refers to which action with respect to the stored state?

Accepted Answer

Introduction / Context: Clear terminology prevents design errors in sequential circuits. Words like “set,” “reset,” “toggle,” and “hold” have precise meanings in the context of latches and flip-flops. Misunderstanding these terms can cause incorrect timing assumptions or flawed state-machine behavior. Here we focus on the meaning of “hold.” Given Data / Assumptions: The device is a latch or flip-flop that can set, reset, or maintain state. No specific technology family is required; the definition is universal. We consider the intended functional behavior, not transient analog edge cases. Concept / Approach: “Hold” explicitly means to retain the previously stored value without change. For a latch, hold occurs when the enable is inactive and the storage element maintains its last state. For a flip-flop, hold describes periods between active triggering edges when the stored state persists. The term does not imply node forcing, metastability, or data transformation; it simply denotes memory retention. Step-by-Step Solution: Identify control condition for no update (e.g., latch enable inactive or between clock edges).Recognize that in this interval the device must preserve the previous Q value.Match the terminology: “hold” equals “no change.”Exclude other actions like set, reset, and toggle by definition. Verification / Alternative check: Consult any standard timing diagram: between active sampling intervals, Q remains constant. Application notes for latches and flip-flops label these intervals as “hold,” confirming the interpretation. Why Other Options Are Wrong: Set or reset: These force a new value; they are changes, not holding. Toggle: This is a deliberate inversion of state, the opposite of holding. Metastable state: A rare, undesired analog condition; not an intended “hold.” Common Pitfalls: Confusing data “hold time” (a timing parameter requiring data stability after a clock edge) with the operational verb “hold”; assuming hold implies gating signals rather than simply the absence of a state update. Final Answer: no change

Question 12

Asynchronous control of a J–K flip-flop: Which statement best characterizes the preset/clear (asynchronous) inputs on a J–K flip-flop?

Accepted Answer

Introduction / Context: Flip-flops often include asynchronous control inputs such as preset (PRE/SET) and clear (CLR/RESET). These inputs override the synchronous data path and are essential for initialization, fault recovery, and forcing known states. Understanding their priority and timing relative to the clock is fundamental for robust sequential design. Given Data / Assumptions: Device: J–K edge-triggered flip-flop with asynchronous PRE and CLR. Active level may be low or high depending on the family, but the logical effect is the same. Design goal: deterministic initialization and override behavior. Concept / Approach: Asynchronous inputs act immediately when asserted, independent of the clock. They also have higher priority than synchronous inputs (J and K), ensuring that when PRE or CLR is asserted, the output goes to the prescribed state regardless of upcoming clock edges. Good practice avoids asserting both active levels simultaneously, which could produce an invalid or unpredictable state. Step-by-Step Solution: Recognize that PRE forces Q = 1 and CLR forces Q = 0 without waiting for a clock edge.Acknowledge precedence: PRE/CLR dominate J and K; the synchronous path is ignored while they are active.Note the usual restriction: do not assert both PRE and CLR active together.Therefore, all listed properties apply to asynchronous inputs. Verification / Alternative check: Datasheet truth tables show that asserting PRE or CLR immediately drives Q, and notes warn against simultaneous activation. Timing diagrams confirm no clock is required for their effect. Why Other Options Are Wrong: Any single statement alone is incomplete; all are true together, making “all of the above” correct. “Affect output only after two clock cycles” is false; asynchronous means no clock is required. Common Pitfalls: Tying PRE and CLR together; forgetting they are often active-low; violating recovery/removal times, which can cause unpredictable behavior when releasing asynchronous signals near clock edges. Final Answer: all of the above

Question 13

Definition of toggle operation in flip-flops: A clocked flip-flop is said to “toggle” when, after a triggering edge, its outputs transition in which manner?

Accepted Answer

Introduction / Context: “Toggle” is a key term used with T flip-flops and J–K flip-flops when J = K = 1. It describes a deterministic inversion of the stored bit on each active clock event. Recognizing this behavior is central to building counters, frequency dividers, and state machines that rely on predictable bit inversion per clock cycle. Given Data / Assumptions: Edge-triggered flip-flop with a toggle condition (e.g., T = 1 or J = K = 1). Outputs are complementary: Q and Q̄. Idealized digital behavior without metastability is assumed. Concept / Approach: Toggle means the next state equals the logical NOT of the current state: Q_next = NOT(Q_current). In J–K terms, with J = K = 1, the excitation table specifies toggling. This property is exploited in ripple and synchronous counters, where each stage toggles to divide frequency or to propagate carries under controlled logic. Step-by-Step Solution: Identify the toggle condition (e.g., T = 1 or J = K = 1).Apply the rule: Q_next = NOT(Q_current) at the active clock edge.Observe that Q̄_next simultaneously becomes NOT(Q_next), preserving complementarity.Conclude that “change to opposite states” is the correct description. Verification / Alternative check: Review J–K excitation tables or T flip-flop characteristic equations; both demonstrate inversion on each qualifying clock. Simulations of binary counters likewise show a divide-by-2 action caused by toggling each clock. Why Other Options Are Wrong: Remain the same: That describes a “hold,” not a toggle. Force to 1 or force to 0: Those are set and reset behaviors, not toggling. High-impedance: Flip-flops do not normally present tri-state outputs. Common Pitfalls: Confusing toggle with asynchronous set/reset; forgetting that toggling happens only at the qualifying clock edge; overlooking setup/hold constraints that must be satisfied to ensure reliable toggling. Final Answer: change to opposite states

Question 14

555 timer in basic astable mode: For a 555 timer configured as a standard astable multivibrator (using two resistors and one capacitor), which element(s) set the duty cycle?

Accepted Answer

Introduction / Context: The ubiquitous 555 timer can generate square or rectangular waves in astable mode. Designers frequently need to set both frequency and duty cycle. In the classic configuration, two resistors (RA and RB) and one capacitor (C) define the waveform characteristics. This question pinpoints which components control duty cycle specifically. Given Data / Assumptions: Standard 555 astable using RA, RB, and C. No diode modifications or symmetry-correction tricks are applied. Thresholds at 1/3 Vcc and 2/3 Vcc apply as usual. Concept / Approach: In the basic astable, the capacitor charges through RA + RB and discharges through RB only. Thus, the high-time T_H depends on (RA + RB) * C, while the low-time T_L depends on RB * C. Because T_H and T_L depend differently on RA and RB, the duty cycle D = T_H / (T_H + T_L) is determined by the ratio of these two resistances, not by the capacitor alone. The capacitor scales both times equally and sets frequency in combination with the resistors, but it does not independently set duty cycle. Step-by-Step Solution: Use standard relations: T_H ≈ 0.693 * (RA + RB) * C and T_L ≈ 0.693 * RB * C.Compute duty cycle D = T_H / (T_H + T_L) = (RA + RB) / (RA + 2*RB).Recognize that only RA and RB appear in the ratio; C cancels out.Therefore, duty cycle is set by the two resistors. Verification / Alternative check: Perform a parametric sweep: vary C while keeping RA and RB constant; the duty cycle remains unchanged while frequency shifts. Vary RA or RB with C fixed; duty cycle changes accordingly. Why Other Options Are Wrong: One resistor or one capacitor: Cannot independently control both T_H and T_L. A resistor and a capacitor: C affects timing, but duty cycle depends on the resistor ratio. Control-voltage pin only: CV can modulate thresholds for special effects, not the basic duty formula. Common Pitfalls: Assuming duty cycle equals 50% by default; neglecting that without a steering diode, perfect symmetry is not achieved; misattributing duty variation to C rather than RA/RB ratio. Final Answer: two resistors

Question 15

J–K pulse-triggered flip-flop with J = K = 1: When both inputs of a J–K pulse-triggered flip-flop are HIGH and a valid clock edge occurs, what is the resulting output action?

Accepted Answer

Introduction / Context: The hallmark of the J–K flip-flop is its toggling behavior when J and K are both asserted. This property allows efficient construction of binary counters and frequency dividers. Knowing the exact outcome under J = K = 1 at the active clock edge is core knowledge in sequential logic. Given Data / Assumptions: Edge-triggered J–K flip-flop (positive or negative edge as specified by device). J = 1 and K = 1 are stable around the triggering edge, satisfying setup/hold. No asynchronous inputs are asserted. Concept / Approach: From the characteristic table, J = K = 1 produces Q_next = NOT(Q_current). This is toggling, meaning the output flips state every valid edge. The behavior is deterministic so long as timing constraints are respected and the inputs are not changing during the aperture window. Step-by-Step Solution: Recall J–K characteristic: J = 0, K = 0 → hold; J = 0, K = 1 → reset; J = 1, K = 0 → set; J = 1, K = 1 → toggle.With J = K = 1, compute Q_next = NOT(Q_current).The complementary output Q̄_next follows as NOT(Q_next).Therefore, the output action is “toggle.” Verification / Alternative check: Simulate a divide-by-2 counter stage using a J–K with J = K tied HIGH; the output frequency is half the input clock, confirming toggling at each edge. Why Other Options Are Wrong: Invalid: The condition is well-defined, not invalid. Not change / remain unchanged: That corresponds to J = K = 0 (hold), not 1,1. Tri-state: Standard flip-flop outputs are driven high/low, not tri-stated. Common Pitfalls: Violating setup/hold times causing race-like symptoms; mistakenly assuming level-sensitive behavior; overlooking asynchronous inputs that could override the synchronous path. Final Answer: toggle

Question 16

Hardware description terminology: In digital design and HDL discussions, a J–K flip-flop is considered a standard building block of clocked sequential logic known as a ________.

Accepted Answer

Introduction / Context: Digital systems are commonly described using hierarchical building blocks. At lower levels, gates and fundamental storage elements are treated as primitives. Recognizing which elements qualify as “logic primitives” helps in understanding libraries, synthesis, and schematic capture conventions across HDL tools and textbooks. Given Data / Assumptions: We are classifying a J–K flip-flop within a design hierarchy. Context is general digital logic and HDL terminology, not a specific vendor syntax. Primitives are basic, reusable components with well-known behavior. Concept / Approach: A “logic primitive” is a fundamental unit available in libraries or inferred by tools, such as gates, latches, and flip-flops. The J–K flip-flop, being a canonical edge-triggered storage element with defined characteristic equations, is routinely treated as a primitive. In contrast, “FUNCTION,” “VARIABLE,” and “PROCESS” are HDL language constructs or data holders, not hardware primitives themselves. Step-by-Step Solution: List primitive examples: AND, OR, NOT, DFF, JKFF, latches.Note that a J–K flip-flop directly maps to hardware behavior, not merely syntax.Recognize that VARIABLES (data objects) and PROCESSES (behavioral blocks) are description mechanisms, not physical primitives.Select “logic primitive” as the correct classification. Verification / Alternative check: Examine library cells for standard-cell ASICs or FPGA inference guides; flip-flops are treated as primitive sequential cells with defined timing arcs and setup/hold requirements. Why Other Options Are Wrong: FUNCTION: An HDL function returns a value; it is not a hardware element by itself. VARIABLE: A storage object in code, not a mapped hardware primitive. PROCESS: A behavioral block in VHDL, not a single hardware cell. Type qualifier: A language feature, not hardware. Common Pitfalls: Confusing HDL semantics with hardware primitives; assuming anything named in code equates to a physical cell; overlooking the difference between description constructs and synthesized elements. Final Answer: logic primitive

Question 17

Astable multivibrator definition and behavior: An astable multivibrator is a circuit that exhibits which set of properties?

Accepted Answer

Introduction / Context: Multivibrators are foundational timing circuits categorized into astable, monostable, and bistable types. Each has distinct stability and triggering characteristics. The astable form is widely used for clock generation, LED blinking, tone production, and general waveform synthesis without an external trigger. Given Data / Assumptions: No external clock or trigger is applied for normal operation. Standard implementations include transistor pairs, op-amp comparators with hysteresis, or the 555 timer. Idealized switching between two quasi-stable voltage levels is considered. Concept / Approach: An astable circuit has no stable resting state. Once powered, it continually transitions between two states, producing a periodic output—hence it is “free-running.” In contrast, a monostable has one stable state and requires a trigger to produce a single pulse, and a bistable has two stable states, requiring inputs to switch between them with no inherent oscillation. Step-by-Step Solution: Identify the absence of a stable state: the system cannot remain indefinitely in one state.Observe that internal feedback and timing components (R and C) force transitions.Conclude the output is a continuous train of pulses or a square/rectangular wave.Thus the correct description is free-running with continuous output. Verification / Alternative check: Prototype a 555 astable with two resistors and one capacitor; measure continuous oscillation on an oscilloscope without providing any trigger. The same observation holds for transistor-based astables and Schmitt-trigger RC oscillators. Why Other Options Are Wrong: Two stable states: That is a bistable multivibrator (flip-flop). Free-running only or continuous output only: Each is partially correct; both properties together define astable behavior succinctly. Requires an external clock: This contradicts the “free-running” nature of astables. Common Pitfalls: Confusing astable with monostable (one-shot) due to similar component counts; assuming a perfect 50% duty cycle without additional circuitry; neglecting supply and component tolerances that affect frequency and duty cycle stability. Final Answer: is free-running and produces a continuous output signal

Question 18

J–K flip-flop configured as a D-type: If a logic signal D is applied to the J input and its complement D̄ is applied to the K input, a J–K flip-flop behaves as which device?

Accepted Answer

Introduction / Context: J–K flip-flops are versatile because appropriate input conditioning can emulate other flip-flop types. One common technique wires the inputs so the device samples a single data line D effectively, reproducing D flip-flop behavior. Recognizing this mapping simplifies design when only J–K elements are available. Given Data / Assumptions: Connections: J = D and K = D̄. Edge-triggered J–K flip-flop with proper setup/hold respected for D. No asynchronous overrides are active. Concept / Approach: From the J–K characteristic table: J = 1, K = 0 sets Q to 1; J = 0, K = 1 resets Q to 0; J = K = 0 holds; J = K = 1 toggles. With J tied to D and K tied to D̄, the pair (J,K) always forms either (1,0) when D = 1 or (0,1) when D = 0. Thus, at each valid clock edge, Q_next equals D, which is exactly the behavior of a D flip-flop. Step-by-Step Solution: If D = 1 → J = 1 and K = 0 → Q_next = 1 (set).If D = 0 → J = 0 and K = 1 → Q_next = 0 (reset).There are no cases with J = K simultaneously under this wiring.Therefore, the device copies the D input at the clock edge, i.e., it behaves as a D flip-flop. Verification / Alternative check: Implement the wiring in a simulator and apply a data waveform to D with clean edges relative to the clock. Observe Q tracks D on active edges exactly like a DFF. This is a classic textbook equivalence used in lab exercises. Why Other Options Are Wrong: S–C or gated S–C: These are not standard flip-flop names and do not match the described mapping. TOGGLE or T with enable: Toggling would require J and K both tied high, not complementary to a data line. Common Pitfalls: Failing to maintain D stable around the clock edge (setup/hold violations); miswiring complements leading to unintended toggling; leaving inputs floating, which can cause unpredictable behavior. Final Answer: D flip-flop

Flip-Flops Questions